Chip Erase

Serial

Downloading

Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.

2.tWLRH_CE is valid for the Chip Erase command.

Both the Flash and EEPROM memory arrays can be programmed using a serial programming bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, PDI (input) and PDO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 45 on page 248, the pin mapping for serial programming is listed. Not all packages use the SPI pins dedicated for the internal Serial Peripheral Interface - SPI.

Serial

Programming Pin

Mapping

Table 45. Pin Mapping Serial Programming

Figure 104. Serial Programming and Verify(1)

+1.8 - 5.5V

VCC

+1.8 - 5.5V(2)

PDI

AVCC

PDO

SCK

XTAL1

RESET

GND

Serial Programming

Algorithm

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

When writing serial data to the AT90USB82/162, data is clocked on the rising edge of SCK.

When reading data from the AT90USB82/162, data is clocked on the falling edge of SCK. See Figure 105 for timing details.

To program and verify the AT90USB82/162 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 47):

1.Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.

2.Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin PDI.

3.The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.

4.The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the address lines 15..8. Before issuing this command, make sure the instruction Load Extended Address Byte has been used to define the MSB of the address. The extended address byte is stored until the command is re-issued, i.e., the command needs only to be issued for the first page, since the memory size is not larger than 64KWord. If polling (RDY/BSY)

is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 46.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming.

5.The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait

at least tWD_EEPROM before issuing the next byte. (See Table 46.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed.

6.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output PDO. When reading the Flash memory, use the instruction Load Extended Address Byte to define the upper address byte, which is not included in the Read Program Memory instruction. The extended address byte is stored until the command is re-issued, i.e., the command needs only to be issued for the first page, since the memory size is not larger than 64KWord.