USB device endpoint registers

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2-0 - EPNUM2:0 Endpoint Number Bits

Set to select the number of the endpoint which shall be accessed by the CPU. See Section , page 193 for more details.

Values greater than 100b are forbidden.

• 7-5 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 4-0 - EPRST4:0 - Endpoint FIFO Reset Bits

Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. See Section , page 192 for more information

Then, cleared by software to complete the reset operation and start using the FIFO.

• 7-6 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 5 - STALLRQ - STALL Request Handshake Bit

Set to request a STALL answer to the host for the next handshake.

Cleared by hardware when a new SETUP is received. Clearing by software has no effect.

See Section , page 195 for more details.

• 4 - STALLRQC - STALL Request Clear Handshake Bit

Set to disable the STALL handshake mechanism.

Cleared by hardware immediately after the set. Clearing by software has no effect.

See Section , page 195 for more details.

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001b: 16 bytes

010b: 32 bytes

011b: 64 bytes

Other : Reserved. Do not use this configuration.

• 3-2 - EPBK1:0 - Endpoint Bank Bits

Set this field according to the endpoint size:

00b: One bank

01b: Double bank

1xb: Reserved. Do not use this configuration.

• 1 - ALLOC - Endpoint Allocation Bit

Set this bit to allocate the endpoint memory.

Clear to free the endpoint memory.

See Section , page 193 for more details.

• 0 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 7 - CFGOK - Configuration Status Flag

Set by hardware when the endpoint X size parameter (EPSIZE) and the bank parametrization (EPBK) are correct compared to the max FIFO capacity and the max number of allowed bank. This bit is updated when the bit ALLOC is set.

If this bit is cleared, the user should reprogram the UECFG1X register with correct EPSIZE and EPBK values.

• 6 - OVERFI - Overflow Error Interrupt Flag

Set by hardware when an overflow error occurs in an isochronous endpoint. An interrupt (EPINTx) is triggered (if enabled).

See Section , page 200 for more details.

Shall be cleared by software. Setting by software has no effect.

• 5 - UNDERFI - Flow Error Interrupt Flag

Set by hardware when an underflow error occurs in an isochronous endpoint. An interrupt (EPINTx) is triggered (if enabled).

See Section , page 200 for more details.

Shall be cleared by software. Setting by software has no effect.

• 4- Reserved

The value read from these bits is always 0. Do not set these bits.

• 3-2 - DTSEQ1:0 - Data Toggle Sequencing Flag

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• 7 - FIFOCON - FIFO Control Bit

For OUT and SETUP Endpoint:

Set by hardware when a new OUT message is stored in the current bank, at the same time than RXOUT or RXSTP.

Clear to free the current bank and to switch to the following bank. Setting by software has no effect.

For IN Endpoint:

Set by hardware when the current bank is free, at the same time than TXIN.

Clear to send the FIFO data and to switch the bank. Setting by software has no effect.

• 6 - NAKINI - NAK IN Received Interrupt Flag

Set by hardware when a NAK handshake has been sent in response of a IN request from the host. This triggers an USB interrupt if NAKINE is sent.

Shall be cleared by software. Setting by software has no effect.

• 5 - RWAL - Read/Write Allowed Flag

Set by hardware to signal:

-for an IN endpoint: the current bank is not full i.e. the firmware can push data into the FIFO,

-for an OUT endpoint: the current bank is not empty, i.e. the firmware can read data from the FIFO.

The bit is never set if STALLRQ is set, or in case of error.

Cleared by hardware otherwise.

This bit shall not be used for the control endpoint.

• 4 - NAKOUTI - NAK OUT Received Interrupt Flag

Set by hardware when a NAK handshake has been sent in response of a OUT/PING request from the host. This triggers an USB interrupt if NAKOUTE is sent.

Shall be cleared by software. Setting by software has no effect.

• 3 - RXSTPI - Received SETUP Interrupt Flag

Set by hardware to signal that the current bank contains a new valid SETUP packet. An interrupt (EPINTx) is triggered (if enabled).

Shall be cleared by software to handshake the interrupt. Setting by software has no effect.

This bit is inactive (cleared) if the endpoint is an IN endpoint.

• 2 - RXOUTI / KILLBK - Received OUT Data Interrupt Flag

Set by hardware to signal that the current bank contains a new packet. An interrupt (EPINTx) is triggered (if enabled).

Shall be cleared by software to handshake the interrupt. Setting by software has no effect.

Kill Bank IN Bit

Set this bit to kill the last written bank.

Cleared by hardware when the bank is killed. Clearing by software has no effect.

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• 7-0 - DAT7:0 -Data Bits

Set by the software to read/write a byte from/to the endpoint FIFO selected by EPNUM.

• 7-0 - BYCT7:0 - Byte Count Bits

Set by the hardware. BYCT7:0 is:

-(for IN endpoint) increased after each writing into the endpoint and decremented after each byte sent,

-(for OUT endpoint) increased after each byte sent by the host, and decremented after each byte read by the software.

• 7-5 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 4-0 - EPINT4:0 - Endpoint Interrupts Bits

Set by hardware when an interrupt is triggered by the UEINTX register and if the corresponding endpoint interrupt enable bit is set.

Cleared by hardware when the interrupt source is served.

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