Set this bit to one by firmware in order to reset the CPU at the next USB reset (without disabling the USB controller). The value of this bit will not be affected by the reset of the CPU generated by a End Of Reset (remains set). This bit is reset when the USB controller is disabled.
Set this bit to zero by firmware otherwise.
• Bit 1- RMWKUP - Remote Wake-up Bit
Set to send an “upstream-resume” to the host for a remote wake-up. The SUSPI bit must be set to allow the remote wake up to be sent.
Cleared by hardware. Clearing by software has no effect.
See Section , page 195 for more details.
• Bit 0 - DETACH - Detach Bit
Set to physically detach de device.
Clear to reconnect the device. See Section , page 194 for more details.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
- |
UPRSMI |
EORSMI |
WAKEUPI |
EORSTI |
SOFI |
- |
SUSPI |
UDINT |
|
|
|
|
|
|
|
|
|
|
Read/W |
R |
R/W |
R/W |
R/W |
R/W |
R/W |
R |
R/W |
|
rite |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Initial |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Value |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6 - UPRSMI - Upstream Resume Interrupt Flag
Set by hardware when the USB controller is sending a resume signal called “Upstream Resume”. This triggers an USB interrupt if UPRSME is set.
Shall be cleared by software (USB clocks must be enabled before). Setting by software has no effect.
• 5 - EORSMI - End Of Resume Interrupt Flag
Set by hardware when the USB controller detects a good “End Of Resume” signal initiated by the host. This triggers an USB interrupt if EORSME is set.
Shall be cleared by software. Setting by software has no effect.
• 4 - WAKEUPI - Wake-up CPU Interrupt Flag
Set by hardware when the USB controller is re-activated by a filtered non-idle signal from the lines (not by an upstream resume). This triggers an interrupt if WAKEUPE is set.
Shall be cleared by software (USB clock inputs must be enabled before). Setting by software has no effect.
See Section , page 194 for more details.
• 3 - EORSTI - End Of Reset Interrupt Flag
Set by hardware when an “End Of Reset” has been detected by the USB controller. This triggers an USB interrupt if EORSTE is set.
Shall be cleared by software. Setting by software has no effect.
• 2 - SOFI - Start Of Frame Interrupt Flag
Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected (every 1 ms). This triggers an USB interrupt if SOFE is set..
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7707A–AVR–01/07
• 7 - ADDEN - Address Enable Bit
Set to activate the UADD (USB address).
Cleared by hardware. Clearing by software has no effect.
See Section , page 194 for more details.
• 6-0 - UADD6:0 - USB Address Bits
Set to configure the device address.
Shall not be cleared.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
- |
- |
- |
- |
- |
FNUM10:8 |
|
|
UD- |
|
|
|
|
|
|
|
|
|
FNUMH |
|
|
|
|
|
|
|
|
|
|
Read/W |
R |
R |
R |
R |
R |
R |
R |
R |
|
rite |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Initial |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Value |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - FNUM10:8 - Frame Number Upper Flag
Set by hardware. These bits are the 3 MSB of the 11-bits Frame Number information. They are provided in the last received SOF packet. FNUM is updated if a corrupted SOF is received.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
FNUM7:0 |
|
|
|
|
|
|
|
UDFNUML |
|
|
|
|
|
|
|
|
|
|
Read/W |
R |
R |
R |
R |
R |
R |
R |
R |
|
rite |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Initial |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Value |
|
|
|
|
|
|
|
|
|
|
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|
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|
|
• 7-0 Frame Number Lower Flag
Set by hardware. These bits are the 8 LSB of the 11-bits Frame Number information.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
- |
- |
- |
FNCERR |
- |
- |
- |
- |
UDMFN |
|
|
|
|
|
|
|
|
|
|
Read/W |
R |
R |
R |
R/W |
R |
R |
R |
R |
|
rite |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Initial |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Value |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
• 7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - FNCERR -Frame Number CRC Error Flag
Set by hardware when a corrupted Frame Number in start of frame packet is received.
This bit and the SOFI interrupt are updated at the same time.
• 3-0 - Reserved
The value read from these bits is always 0. Do not set these bits.
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7707A–AVR–01/07