If the endpoint uses 2 banks, the second one can be read by the HOST while the current is

being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already

ready (free) and TXINI is set immediately.

Abort

An “abort” stage can be produced by the host in some situations:

• In a control transaction: ZLP data OUT received during a IN stage,

• In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN

stage on the IN endpoint

• ...

The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to per-

form the following operations:

Table 18. Abort flow

Abort done

Isochronous mode

Underflow

An underflow can occur during IN stage if the host attempts to read a bank which is empty. In

this situation, the UNDERFI interrupt is triggered.

An underflow can also occur during OUT stage if the host send a packet while the banks are

already full. Typically, he CPU is not fast enough. The packet is lost.

It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU

should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)

CRC Error

A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In

this situation, the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt

from being triggered.

Overflow

In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if

the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI

interrupt is triggered (if enabled). The packet is hacknowledged and the RXOUTI interrupt is also

triggered (if enabled). The bank is filled with the first bytes of the packet.

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