USB Device Operating modes

Introduction

Power-on and reset

The USB device controller supports full speed data transfers. In addition to the default control endpoint, it provides four other endpoints, which can be configured in control, bulk, interrupt or isochronous modes:

•Endpoint 0: programmable size FIFO up to 64 bytes, default control endpoint

•Endpoints 1and 2: programmable size FIFO up to 64 bytes.

•Endpoints 3 and 4: programmable size FIFO up to 64 bytes in ping-pong mode.

The controller starts in the “idle” mode. In this mode, the pad consumption is reduced to the minimum.

The next diagram explains the USB device controller main states on power-on:

Figure 83. USB device controller states after reset

<any other

USBE=0 state>

Endpoint reset

The reset state of the Device controller is:

•the macro clock is stopped in order to minimize the power consumption (FRZCLK set),

•the USB device controller internal state is reset (all the registers are reset to their default value. Note that DETACH is set.)

•the endpoint banks are reset

•the D+ pull up are not activated (mode Detach)

The D+ pull-up will be activated as soon as the DETACH bit is cleared.

The macro is in the ‘Idle’ state after reset with a minimum power consumption and does not need to have the PLL activated to enter in this state.

The USB device controller can at any time be reset by clearing USBE.

An endpoint can be reset at any time by setting in the UERST register the bit corresponding to the endpoint (EPRSTx). This resets:

•the internal state machine on that endpoint,

•the Rx and Tx banks are cleared and their internal pointers are restored,

•the UEINTX, UESTA0X and UESTA1X are restored to their reset value.

The data toggle field remains unchanged.

The other registers remain unchanged.

The endpoint configuration remains active and the endpoint is still enabled.

Endpoint activation

Address Setup

Suspend, Wake-up

and Resume

Detach

A clear of EPEN acts as an endpoint reset (see Section , page 192 for more details). It also performs the next operation:

•The configuration of the endpoint is kept (EPSIZE, EPBK, ALLOC kept)

•It resets the data toggle field.

•The DPRAM memory associated to the endpoint is still reserved.

See Section , page 186 for more details about the memory allocation/reorganization.

The USB device address is set up according to the USB protocol:

•the USB device, after power-up, responds at address 0

•the host sends a SETUP command (SET_ADDRESS(addr)),

•the firmware records that address in UADD, but keep ADDEN cleared,

•the USB device sends an IN command of 0 bytes (IN 0 Zero Length Packet) to acknowledge the transaction,

•then, the firmware may enable the USB device address by setting ADDEN. The only accepted address by the controller is the one stored in UADD.

ADDEN and UADD shall not be written at the same time.

UADD contains the default address 00h after a power-up or an USB reset.

ADDEN is cleared by hardware:

•after a power-up reset,

•when an USB reset is received,

•or when the macro is disabled (USBE cleared)

When this bit is cleared, the default device address 00h is used.

After a period of 3 ms during which the USB line was inactive (J state), the controller setn the SUSPI flag and triggers the corresponding interrupt if enabled. The firmware may then set the FRZCLK bit.

The CPU can also, depending on software architecture, disable the PLL and/or enter in the idle mode to reduce the power consumption (especially in a bus powered application).

There are two ways to recover from the “Suspend” mode:

•First one is to clear the FRZCLK bit. This is possible if the CPU is not in the Idle mode.

•Second way, if the CPU is “idle”, is to enable the WAKEUPI interrupt (WAKEUPE set). Then, as soon as an non-idle signal is seen by the controller, the WAKEUPI interrupt is triggered. The firmware shall then clear the FRZCLK bit to restart the transfer.

There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the WAKEUPI interrupt is triggered as soon as there are non-idle patterns on the data lines. Thus, the WAKEUPI interrupt can occurs even if the controller is not in the “suspend” mode.

When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was already set, it is cleared by hardware.

When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is cleared by hardware.

The reset value of the DETACH bit is 1.

It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit (the line discharge time must be taken in account).