Figure 82. Pad behaviour
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USBE=1 |
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& DETACH=0 |
Idle mode |
& |
suspend |
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USBE=0 |
Active mode |
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| suspend |
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The SUSPI flag indicated that a suspend state has been detected on the USB bus. This flag automatically put the USB pad in Idle. The detection of a non-idle event sets the WAKEUPI flag and wakes-up the USB pad.
Suspend detected = USB pad power down |
Clear Suspend by software |
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Clear Resume by software
Resume = USB pad wake-up
PAD status
Moreover, the pad can also be put in the “idle” mode if the DETACH bit is set. It come back in the active mode when the DETACH bit is cleared.
D+/D- Read/write The level of D+ and D- can be read and written using the UPOE register. The USB controller has to be enabled to write a value. For read operation, the USB controller can be enabled or disabled.
Registers description
USB general registers
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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USBE |
- |
FRZLK |
- |
- |
- |
- |
- |
USBCON |
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Read/Writ |
R/W |
R |
R/W |
R |
R |
R |
R |
R |
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e |
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188
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Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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Initial Val- |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
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ue |
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• 7 – USBE: USB macro Enable Bit
Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the
USB transceiver and to disable the USB controller clock inputs.
• 6 – Reserved
The value read from this bit is always 0. Do not set this bit.
• 5 – FRZCLK: Freeze USB Clock Bit
Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power consumption. Clear to enable the clock inputs.
• 4-0 – Reserved
The value read from these bits is always 0. Do not set these bits.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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DPACC |
- |
- |
- |
- |
- |
- |
- |
UDPAD- |
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DH |
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Read/Wr |
R/W |
R |
R |
R |
R |
R |
R |
R |
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ite |
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Initial |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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Value |
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• 7 – DPACC: DPRAM Direct Access Bit
Set this bit to directly read the content the Dual-Port RAM (DPR) data through the UEDATX or
UPDATX registers. See Section , page 185 for more details.
Clear this bit for normal operation and access the DPR through the endpoint FIFO.
• 6-0 – Reserved
The value read from these bits is always 0. Do not set these bits.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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DPADD7:0 |
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UDPAD- |
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DL |
Read/Wr |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
ite |
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Initial |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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Value |
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• 7-0 – DPADD7:0: DPRAM Address Low Bit
DAPDD7:0 is the least significant part of DPADD.
189
7707A–AVR–01/07
USB/PS2 Software Output Enable register
– UPOE
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Bit |
7 |
6 |
5 |
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4 |
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3 |
2 |
1 |
0 |
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UPWE1 |
UPWE0 |
UPDRV |
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UPDRV |
SCKI |
DATAI |
DPI |
DMI |
UPOE |
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1 |
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0 |
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Read/Write |
R/W |
R/W |
R/W |
R/W |
R |
R |
R |
R |
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Initial Value |
0 |
0 |
0 |
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0 |
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0 |
0 |
0 |
0 |
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• Bit 7:6 – UPOE[1:0]: USB/PS2 Output enable
Set these bits with the following configuration to enable or disable the USB/PS2 software drive. UPOE1 - UPOE0
0 - 0 : Direct drive is disabled.
0 - 1 : Reserved
1 - 0 : Direct drive of DP/DM with USB levels (UPDRV[1:0] values) 1 - 1 : Direct drive of DP/DM with PS/2 levels (UPDRV[1:0] values)
• Bit 5:4 – UPDRV[1:0] : USB/PS2 direct drive values
Write in UPDRV1 the value to write on D+/SCK following the UPOE[1:0] configuration.
Write in UPDRV0 the value to write on D-/DATA following the UPOE[1:0] configuration.
• Bit 3 – SCKI : SCK Input value
This bit is set to one by hardware if a ‘1’ is read on SCK (PS/2 pad).
This bit is set to zero by hardware if a ‘0’ is read on SCK (PS/2 pad).
• Bit 2 – DATAI : DATA Input value
This bit is set to one by hardware if a ‘1’ is read on DATA (PS/2 pad).
This bit is set to zero by hardware if a ‘0’ is read on DATA (PS/2 pad).
• Bit 1 – DPI : D+ Input value
This bit is set to one by hardware if a ‘1’ is read on D+ (USB pad).
This bit is set to zero by hardware if a ‘0’ is read on D+ (USB pad).
• Bit 0 – DMI : D- Input value
This bit is set to one by hardware if a ‘1’ is read on D- (USB pad).
This bit is set to zero by hardware if a ‘0’ is read on D- (USB pad).
190
