Power modes

Freeze clock

Memory access capability

The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the following registers:

•USBCON,

•DPRAM direct access registers (DPADD7:0, UEDATX)

•UDCON (detach, ...)

•UDINT

•UDIEN

Moreover, when FRZCLK is set, only the asynchronous interrupt may be triggered :

•WAKEUPI

The CPU has the possibility to directly access to the USB internal memory (DPRAM).

The memory access mode is performed using 2 sfr’s: UDPADDH and UDPADDL.

To enter in this mode:

•the USBE bit must be cleared.

•the DPACC bit and the base address DPADD7:0 must be set.

Even if the USBE bit is cleared, the DPACC bit and DPADD7:0 field can be used by the firmware.

Then, a read or a write in UEDATX (device mode) is performed according to DPADD7:0 and the base address DPADD7:0 field is automatically increased. The endpoint FIFO pointers and the value of the UENUM registers are discarded in this mode.

The aim of this functionality is to use the DPRAM as extra-memory.

Memory management

186

When using this mode, there is no influence over the USB controller.

Unused

[DPADDL]

Endpoint 1 to N

Endpoint 0

USB DPRAM

The controller does only support the following memory allocation management.

The reservation of an Endpoint can only be made in the increasing order (Endpoint 0 to the last Endpoint). The firmware shall thus configure them in the same order.

The reservation of an Endpoint “ki” is done when its ALLOC bit is set. Then, the hardware allocates the memory and insert it between the Endpoints “ki-1” and “ki+1”. The “ki+1” Endpoint

memory “slides” up and its data is lost. Note that the “ki+2” and upper Endpoint memory does not slide.

Clearing an Endpoint enable (EPEN) does not clear either its ALLOC bit, or its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear ALLOC. Then, the “ki+1” Endpoint memory automatically “slides” down. Note that the “ki+2” and upper Endpoint memory does not slide.

The following figure illustrates the allocation and reorganization of the USB memory in a typical example:

PAD suspend

•First, Endpoint 0 to Endpoint 4 are configured, in the growing order. The memory of each is reserved in the DPRAM.

•Then, the Endpoint 2is disabled (EPEN=0), but its memory reservation is internally kept by the controller.

•Its ALLOC bit is cleared: the Endpoint 3 “slides” down, but the Endpoint 4 does not “slide”.

•Finally, the firmware chooses to reconfigure the Endpoint 2, but with a bigger size. The controller reserved the memory after the endpoint 1 memory and automatically “slide” the Endpoint 3. The Endpoint 4 does not move and a memory conflict appear, in that both Endpoint 3 and 4 use a common area. The data of those endpoints are potentially lost.

Note that :

•the data of Endpoint 0 are never lost whatever the activation or deactivation of the higher Endpoint. Its data is lost if it is deactivated.

•Deactivate and reactivate the same Endpoint with the same parameters does not lead to a “slide” of the higher endpoints. For those endpoints, the data are preserved.

•CFGOK is set by hardware even in the case that there is a “conflict” in the memory allocation.

The next figures illustrates the pad behaviour:

•In the “idle” mode, the pad is put in low power consumption mode.

•In the “active” mode, the pad is working.