- •Features
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •D-/SDATA
- •UGND
- •UVCC
- •UCAP
- •RESET/PC1/dW
- •XTAL1
- •XTAL2/PC0
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •TABLE 1.
- •TABLE 2.
- •AVR AT90USB82/162 Memories
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Switch
- •Exemple of use
- •Swith from external clock to RC clock
- •Switch from RC clock to external clock
- •Clock Sources
- •Default Clock Source
- •External Clock
- •Internal PLL for USB interface
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •USB Reset
- •Watchdog Timer
- •TABLE 2.
- •TABLE 2.
- •Interrupts
- •TABLE 2.
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •TABLE 3.
- •Unconnected Pins
- •Alternate Port Functions
- •Register Description for I/O-Ports
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •TABLE 2.
- •TABLE 2.
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •TABLE 2.
- •TABLE 3.
- •TABLE 4.
- •Parity Generator
- •TABLE 3.
- •TABLE 2.
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •TABLE 2.
- •Using MPCMn
- •Receiver Flow Control
- •Overview
- •Clock Generation
- •Frame Formats
- •TABLE 2.
- •Data Transfer
- •TABLE 3.
- •USB controller
- •Features
- •Block Diagram
- •Typical Application Implementation
- •Device mode
- •Bus Powered device
- •Introduction
- •Interrupts
- •Power modes
- •Idle mode
- •Power down
- •Freeze clock
- •Memory access capability
- •Memory management
- •PAD suspend
- •D+/D- Read/write
- •Registers description
- •USB general registers
- •USB Software Operating modes
- •USB Device Operating modes
- •Introduction
- •Power-on and reset
- •Endpoint reset
- •USB reset
- •Endpoint selection
- •Endpoint activation
- •Address Setup
- •Detach
- •Remote Wake-up
- •STALL request
- •Special consideration for Control Endpoints
- •STALL handshake and Retry mechanism
- •CONTROL endpoint management
- •Control Write
- •Control Read
- •Overview
- •“Manual” mode
- •Detailed description
- •IN endpoint management
- •“Manual” mode
- •Detailed description
- •Abort
- •Isochronous mode
- •Underflow
- •CRC Error
- •Overflow
- •Interrupts
- •Registers
- •USB device general registers
- •USB device endpoint registers
- •Characteristics
- •Analog Comparator
- •Application Section
- •Boot Reset Fuse
- •Simple Assembly Code Example for a Boot Loader
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Maximum speed vs. VCC
- •Supply Current of IO modules
- •Example 1
- •Example 2
- •Example 3
- •Instruction Set Summary
- •Packaging Information
- •TQFP32
Typical Application Implementation
Depending on the USB operating mode and target application power supply, the AT90USB82/162 requires different hardware typical implementations.
Figure 75. Operating modes versus frequency and power-supply
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VCC (V) |
Max |
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Operating Frequency (MHz) |
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5.5 |
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4.5 |
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16 MHz |
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USB compliant, |
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with internal regulator |
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3.6 |
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8 MHz |
3.4 |
USB compliant, |
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without internal regulator |
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3.0 |
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2.7 |
USB not operational |
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2 MHz |
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VCC min |
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0 |
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Device mode
Bus Powered device
Figure 76. Typical Bus powered application with 5V I/O
VCC
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UCAP |
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1µF |
VBUS |
UVCC |
UDM |
D+ |
UDP |
D- |
UVSS |
UVSS |
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VSS |
XTAL1 XTAL2
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Figure 77. Typical Bus powered application with 3V I/O
VCC
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UCAP |
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1µF |
VBUS |
UVCC |
UDM |
D+ |
UDP |
D- |
UVSS |
UVSS |
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VSS |
XTAL1 XTAL2
Serial resistors on USB Data lines should have 22 Ohms value (+/-5%).
Ucap capacitor should have 1µF (+/- 10%) value for correct operation.
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General Operating
Modes
Introduction |
The USB controller is disabled and reset after a hardware reset generated by: |
–Power on reset
–External reset
–Watchdog reset
–Brown out reset
–debugWIRE reset
But another available and optionnal reset source is :
–USB End Of Reset
In this case, the USB controller is reset, but not disabled (so that the device remains attached).
Power-on and reset The next diagram explains the USB controller main states on power-on:
Figure 78. USB controller states after reset
Clockstopped |
USBE=0 |
<anyother |
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FRZCLK=1 |
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state> |
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Macrooff |
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Reset |
HWRESET |
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(exceptedfromEOR) |
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USBE=1 |
USBE=0 |
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USBE=0 |
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Dev ice
HW RESETfrom EOR
When the USB controller is in reset state:
• USBE is not set
• the USB controller clock is stopped in order to minimize the power consumption (FRZCLK=1),
• the USB controller is disabled,
• USB is in the suspend mode,
• the Device USB controllers internal state is reset.
• The DPACC bit and the DPADD10:0 field can be set by software. The DPRAM is not
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cleared. |
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• The SPDCONF bits can be set by software. |
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After setting USBE, the USB Controller enters in the Device state. |
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The USB Controller can at any time be ‘stopped’ by clearing USBE. In fact, clearing USBE acts |
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as an hardware reset on the USB macro. |
Interrupts |
Two interrupts vectors are assigned to USB controller. |
182 |
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Figure 79. USB Interrupt System
USB General
USB Device Interrupt Vector
Interrupt
USB Endpoint/Pipe
Interrupt Vector
Endpoint
Interrupt
The macro distinguishes between USB General events in opposition with USB Endpoints events that are relevant with data transfers relatives to each endpoint.
Figure 80. USB General interrupt vector sources
UPRSMI
UDINT.6
UPRSME
UDIEN.6
EORSMI
UDINT.5
EORSME
UDIEN.5
WAKEUPI
UDINT.4
WAKEUPE
UDIEN.4
EORSTI
UDINT.3
EORSTE
UDIEN.3
SOFI
UDINT.2
SOFE
UDIEN.2
SUSPI
UDINT.0
SUSPE
UDIEN.0
USB General
Interrupt Vector
Asynchronous Interrupt source
(allows the CPU to wake up from power down mode)
Each of these interupts are time-relative events that will be detected only if the USB clock is enabled (FRZCLK bit set), except for the WAKEUP interrupt that will trigger each time a state change is detected on the data lines.
This asynchronous interrupt WAKEUP allows to wake-up a device that is in power-down mode, generally after that the USB has entered the Suspend state.
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Figure 81. USB Endpoint Interrupt vector sources
Endpoint 4
Endpoint 3
Endpoint 2
Endpoint 1
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Endpoint 0 |
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OVERFI |
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UESTAX.6 |
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UNDERFI |
FLERRE |
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UESTAX.5 |
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UEIENX.7 |
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NAKINI |
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UEINTX.6 |
NAKINE |
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UEIENX.6 |
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NAKOUTI |
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UEINTX.4 |
TXSTPE |
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UEIENX.4 |
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RXSTPI |
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EPINT |
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UEINTX.3 |
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TXOUTE |
UEINT.X |
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UEIENX.3 |
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RXOUTI |
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UEINTX.2 |
RXOUTE |
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UEIENX.2 |
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STALLEDI |
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UEINTX.1 |
STALLEDE |
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UEIENX.1 |
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TXINI |
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UEINTX.0 |
TXINE |
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UEIENX.0 |
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USB Endpoint
Interrupt Vector
Each endpoint has 8 interrupts sources associated with flags, and each source can be enabled or not to trigger the corresponding endpoint interrupt.
If, for an endpoint, at least one of the sources is enabled to trigger interrupt, the corresponding event(s) will make the program branch to the USB Endpoint Interrupt vector. The user may determine the source (endpoint) of the interrupt by reading the UEINT register, and then handle the event detected by polling the different flags.
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