- •Features
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •D-/SDATA
- •UGND
- •UVCC
- •UCAP
- •RESET/PC1/dW
- •XTAL1
- •XTAL2/PC0
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •TABLE 1.
- •TABLE 2.
- •AVR AT90USB82/162 Memories
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Switch
- •Exemple of use
- •Swith from external clock to RC clock
- •Switch from RC clock to external clock
- •Clock Sources
- •Default Clock Source
- •External Clock
- •Internal PLL for USB interface
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •USB Reset
- •Watchdog Timer
- •TABLE 2.
- •TABLE 2.
- •Interrupts
- •TABLE 2.
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •TABLE 3.
- •Unconnected Pins
- •Alternate Port Functions
- •Register Description for I/O-Ports
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •TABLE 2.
- •TABLE 2.
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •TABLE 2.
- •TABLE 3.
- •TABLE 4.
- •Parity Generator
- •TABLE 3.
- •TABLE 2.
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •TABLE 2.
- •Using MPCMn
- •Receiver Flow Control
- •Overview
- •Clock Generation
- •Frame Formats
- •TABLE 2.
- •Data Transfer
- •TABLE 3.
- •USB controller
- •Features
- •Block Diagram
- •Typical Application Implementation
- •Device mode
- •Bus Powered device
- •Introduction
- •Interrupts
- •Power modes
- •Idle mode
- •Power down
- •Freeze clock
- •Memory access capability
- •Memory management
- •PAD suspend
- •D+/D- Read/write
- •Registers description
- •USB general registers
- •USB Software Operating modes
- •USB Device Operating modes
- •Introduction
- •Power-on and reset
- •Endpoint reset
- •USB reset
- •Endpoint selection
- •Endpoint activation
- •Address Setup
- •Detach
- •Remote Wake-up
- •STALL request
- •Special consideration for Control Endpoints
- •STALL handshake and Retry mechanism
- •CONTROL endpoint management
- •Control Write
- •Control Read
- •Overview
- •“Manual” mode
- •Detailed description
- •IN endpoint management
- •“Manual” mode
- •Detailed description
- •Abort
- •Isochronous mode
- •Underflow
- •CRC Error
- •Overflow
- •Interrupts
- •Registers
- •USB device general registers
- •USB device endpoint registers
- •Characteristics
- •Analog Comparator
- •Application Section
- •Boot Reset Fuse
- •Simple Assembly Code Example for a Boot Loader
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Maximum speed vs. VCC
- •Supply Current of IO modules
- •Example 1
- •Example 2
- •Example 3
- •Instruction Set Summary
- •Packaging Information
- •TQFP32
SPI Data Modes
and Timing
Frame Formats
172
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 73. Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn functionality is summarized in Table 14. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Table 14. UCPOLn and UCPHAn Functionality-
UCPOLn |
UCPHAn |
SPI Mode |
Leading Edge |
Trailing Edge |
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0 |
0 |
0 |
Sample (Rising) |
Setup (Falling) |
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0 |
1 |
1 |
Setup (Rising) |
Sample (Falling) |
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1 |
0 |
2 |
Sample (Falling) |
Setup (Rising) |
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1 |
1 |
3 |
Setup (Falling) |
Sample (Rising) |
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Figure 73. UCPHAn and UCPOLn data transfer timing diagrams.
UCPHA=1 |
UCPOL=0 |
UCPOL=1 |
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XCK |
XCK |
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Data setup (TXD) |
Data setup (TXD) |
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UCPHA=0 |
Data sample (RXD) |
Data sample (RXD) |
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XCK |
XCK |
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Data setup (TXD) |
Data setup (TXD) |
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Data sample (RXD) |
Data sample (RXD) |
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats:
•8-bit data with MSB first
•8-bit data with LSB first
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. When a complete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state.
The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will then signal that the 16-bit value has been shifted out.
7707A–AVR–01/07
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USART MSPIM |
The USART in MSPIM mode has to be initialized before any communication can take place. The |
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Initialization |
initialization process normally consists of setting the baud rate, setting master mode of operation |
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(by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the |
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Receiver. Only the transmitter can operate independently. For interrupt driven USART opera- |
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tion, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when |
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doing the initialization. |
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Note: To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be |
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zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the |
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UBRRn must then be written to the desired value after the transmitter is enabled, but before the |
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first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces- |
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sary if the initialization is done immediately after a reset since UBRRn is reset to zero. |
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Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that |
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there is no ongoing transmissions during the period the registers are changed. The TXCn Flag |
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can be used to check that the Transmitter has completed all transfers, and the RXCn Flag can |
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be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag |
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must be cleared before each transmission (before UDRn is written) if it is used for this purpose. |
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The following simple USART initialization code examples show one assembly and one C func- |
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tion that are equal in functionality. The examples assume polling (no interrupts enabled). The |
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baud rate is given as a function parameter. For the assembly code, the baud rate parameter is |
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assumed to be stored in the r17:r16 registers. |
173
7707A–AVR–01/07
