- •Features
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •D-/SDATA
- •UGND
- •UVCC
- •UCAP
- •RESET/PC1/dW
- •XTAL1
- •XTAL2/PC0
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •TABLE 1.
- •TABLE 2.
- •AVR AT90USB82/162 Memories
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Switch
- •Exemple of use
- •Swith from external clock to RC clock
- •Switch from RC clock to external clock
- •Clock Sources
- •Default Clock Source
- •External Clock
- •Internal PLL for USB interface
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •USB Reset
- •Watchdog Timer
- •TABLE 2.
- •TABLE 2.
- •Interrupts
- •TABLE 2.
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •TABLE 3.
- •Unconnected Pins
- •Alternate Port Functions
- •Register Description for I/O-Ports
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •TABLE 2.
- •TABLE 2.
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •TABLE 2.
- •TABLE 3.
- •TABLE 4.
- •Parity Generator
- •TABLE 3.
- •TABLE 2.
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •TABLE 2.
- •Using MPCMn
- •Receiver Flow Control
- •Overview
- •Clock Generation
- •Frame Formats
- •TABLE 2.
- •Data Transfer
- •TABLE 3.
- •USB controller
- •Features
- •Block Diagram
- •Typical Application Implementation
- •Device mode
- •Bus Powered device
- •Introduction
- •Interrupts
- •Power modes
- •Idle mode
- •Power down
- •Freeze clock
- •Memory access capability
- •Memory management
- •PAD suspend
- •D+/D- Read/write
- •Registers description
- •USB general registers
- •USB Software Operating modes
- •USB Device Operating modes
- •Introduction
- •Power-on and reset
- •Endpoint reset
- •USB reset
- •Endpoint selection
- •Endpoint activation
- •Address Setup
- •Detach
- •Remote Wake-up
- •STALL request
- •Special consideration for Control Endpoints
- •STALL handshake and Retry mechanism
- •CONTROL endpoint management
- •Control Write
- •Control Read
- •Overview
- •“Manual” mode
- •Detailed description
- •IN endpoint management
- •“Manual” mode
- •Detailed description
- •Abort
- •Isochronous mode
- •Underflow
- •CRC Error
- •Overflow
- •Interrupts
- •Registers
- •USB device general registers
- •USB device endpoint registers
- •Characteristics
- •Analog Comparator
- •Application Section
- •Boot Reset Fuse
- •Simple Assembly Code Example for a Boot Loader
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Maximum speed vs. VCC
- •Supply Current of IO modules
- •Example 1
- •Example 2
- •Example 3
- •Instruction Set Summary
- •Packaging Information
- •TQFP32
AT90USB82/162
Overview
The AT90USB82/162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90USB82/162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
|
PD7 - PD0 |
PC7 - PC0 |
PB7 - PB0 |
XTAL1 |
XTAL2 |
RESET |
||
|
|
|
|
|
|
|||
- |
PORTD DRIVERS |
PORTC DRIVERS |
PORTB DRIVERS |
|
|
|||
+ |
|
|
|
|
|
|
|
|
ANALOG COMPARATOR |
DATA REGISTER |
DATA DIR. |
DATA REGISTER |
DATA DIR. |
DATA REGISTER |
DATA DIR. |
|
|
PORTD |
REG. PORTD |
PORTC |
REG. PORTC |
PORTB |
REG. PORTB |
|
|
|
|
|
|
8-BIT DA TA BUS |
|
|
|
||
VCC |
|
|
POR - BOD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESET |
INTERNAL |
|
|
|
|
GND |
|
|
|
CALIB. OSC |
|
|
|
|
|
|
|
OSCILLATOR |
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
WATCHDOG |
OSCILLATOR |
|
|
|
|
|
|
|
|
|
|
|
|
|
Debug-Wire |
PROGRAM |
STACK |
TIMER |
|
|
|
|
|
|
|
|
|
|
|||
|
COUNTER |
POINTER |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
ON-CHIP DEBUG |
PROGRAM |
SRAM |
MCU CONTROL |
TIMING AND |
|
|
|
|
FLASH |
|
REGISTER |
CONTROL |
|
|
|
|
|
PROGRAMMING |
INSTRUCTION |
GENERAL |
TIMER/ |
|
|
|
|
|
LOGIC |
REGISTER |
COUNTERS |
|
|
|
|
|
|
PURPOSE |
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
REGISTERS |
|
|
|
|
UVcc |
|
|
|
X |
|
|
|
|
|
|
|
INSTRUCTION |
Y |
INTERRUPT |
|
|
ON-CHIP |
|
|
|
DECODER |
Z |
UNIT |
|
|
3.3V |
|
|
|
|
|
|
|
|
REGULATOR |
|
|
|
|
|
|
|
|
|
UCap |
|
|
CONTROL |
ALU |
EEPROM |
|
|
|
1uF |
|
|
LINES |
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PLL |
|
|
|
|
|
|
STATUS |
|
|
|
|
|
|
|
|
REGISTER |
|
|
|
|
D+/SCK |
|
|
|
|
|
USB |
|
|
|
|
|
|
|
|
|
|
D-/SDATA |
|
|
|
|
|
|
|
|
|
|
|
USART1 |
SPI |
|
|
PS/2 |
|
|
|
3
7707A–AVR–03/07
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The AT90USB82/162 provides the following features: 8K / 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 22 general purpose I/O lines, 32 general purpose working registers, two flexible Timer/Counters with compare modes and PWM, one USART, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, debugWIRE interface, also used for accessing the On-chip Debug system and programming and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, the main Oscillator continues to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an on-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90USB82/162 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The AT90USB82/162 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
4 AT90USB82/162 
7707A–AVR–03/07
