
- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •System Control and Reset
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watch Dog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •Port E Data Register – PORTE
- •Port F Data Register – PORTF
- •Port G Data Register – PORTG
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •16-bit Timer/Counter Register Description
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Multi-master Bus Systems, Arbitration and Synchronization
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Section – BLS
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •2-wire Serial Interface Characteristics
- •ADC Characteristics - Preliminary Data
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information

Figure 138. Programming the EEPROM Waveforms
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K |
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A |
G |
B |
C |
E |
B |
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E |
L |
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DATA |
$10 |
ADDR. HIGH ADDR. LOW |
DATA |
XX |
ADDR. LOW |
DATA |
XX |
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XA1 |
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XA0 |
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BS1 |
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XTAL1 |
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WR |
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RDY/BSY |
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RESET |
+12V |
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OE |
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PAGEL |
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BS2 |
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Reading the Flash |
The algorithm for reading the Flash memory is as follows (refer to “Programming the |
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Flash” on page 285 for details on Command and Address loading): |
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1.A: Load Command “0000 0010”.
2.G: Load Address High Byte ($00 - $FF)
3.B: Load Address Low Byte ($00 - $FF)
4.Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5.Set BS1 to “1”. The Flash word high byte can now be read at DATA.
6.Set OE to “1”.
Reading the EEPROM |
The algorithm for reading the EEPROM memory is as follows (refer to “Programming the |
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Flash” on page 285 for details on Command and Address loading): |
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1. |
A: Load Command “0000 0011”. |
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2. |
G: Load Address High Byte ($00 - $FF) |
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3. |
B: Load Address Low Byte ($00 - $FF) |
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Set |
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to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at |
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OE |
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DATA. |
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5. |
Set |
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to “1”. |
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OE |
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Programming the Fuse Low |
The algorithm for programming the Fuse Low bits is as follows (refer to “Programming |
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Bits |
the Flash” on page 285 for details on Command and Data loading): |
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1. |
A: Load Command “0100 0000”. |
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C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. |
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Give |
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to go high. |
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WR |
a negative pulse and wait for RDY/BSY |
288 ATmega128(L)
2467B–09/01

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ATmega128(L) |
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The algorithm for programming the Fuse high bits is as follows (refer to “Programming |
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Programming the Fuse High |
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Bits |
the Flash” on page 285 for details on Command and Data loading): |
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1. |
A: Load Command “0100 0000”. |
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C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. |
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3. |
Set BS1 to '1'. This selects high data byte. |
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4. |
Give |
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to go high. |
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WR |
a negative pulse and wait for RDY/BSY |
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5. |
Set BS1 to '0'. This selects low data byte. |
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Programming the Extended |
The algorithm for programming the Extended Fuse bits is as follows (refer to “Program- |
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Fuse Bits |
ming the Flash” on page 285 for details on Command and Data loading): |
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1. |
A: Load Command “0100 0000”. |
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C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. |
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3. |
Set BS2 to “1” and BS1 to “0”. This selects extended data byte. |
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4. |
Give |
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to go high. |
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WR |
a negative pulse and wait for RDY/BSY |
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5. |
Set BS2 to “0”. This selects low data byte. |
Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 285 for details on Command and Data loading):
1.A: Load Command “0010 0000”.
2.C: Load Data Low Byte. Bit n = “0” programs the Lock bit.
3.Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
Reading the Fuse and Lock |
The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming |
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the Flash” on page 285 for details on Command loading): |
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A: Load Command “0000 0100”. |
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Set |
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to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can |
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OE |
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now be read at DATA (“0” means programmed). |
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3. |
Set |
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to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can |
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OE |
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now be read at DATA (“0” means programmed). |
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4. |
Set |
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to “0”, BS2 to “1” and BS1 to “0”. The status of the Extended Fuse bits |
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OE |
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can now be read at DATA (“0” means programmed). |
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5. |
Set |
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to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be |
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OE |
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read at DATA (“0” means programmed). |
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6. |
Set |
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OE |
289
2467B–09/01

Figure 139. Mapping Between BS1, BS2 and the Fuseand Lock Bits During Read
Fuse Low Byte |
0 |
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0 |
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Extended Fuse byte |
1 |
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BS2 |
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DATA |
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Lock bits |
0 |
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1 |
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BS1 |
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Fuse high byte |
1 |
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BS2
Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for details on Command and Address loading):
1.A: Load Command “0000 1000”.
2.B: Load Address Low Byte ($00 - $02).
3.Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4.Set OE to “1”.
Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to Programming the Flash for details on Command and Address loading):
1.A: Load Command “0000 1000”.
2.B: Load Address Low Byte, $00.
3.Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4.Set OE to “1”.
Parallel Programming |
Figure 140. Parallel Programming Timing, Including some General Timing |
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Characteristics |
Requirements |
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tXLWL |
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XTAL1 |
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tXHXL |
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Data & Contol |
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tDVXH |
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tXLDX |
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(DATA, XA0/1, BS1, BS2) |
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tBVPH |
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tPLBX |
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t BVWL |
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tWLBX |
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PAGEL |
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tPHPL |
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tWL WH |
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WR |
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tPLWL |
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WLRL |
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RDY/BSY |
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tWLRH |
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290 ATmega128(L)
2467B–09/01

ATmega128(L)
Figure 141. Parallel Programming Timing, Loading Sequence with Timing
Requirements
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LOAD ADDRESS |
LOAD DATA |
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LOAD DATA LOAD DATA |
LOAD ADDRESS |
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(LOW BYTE) |
(LOW BYTE) |
(HIGH BYTE) |
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(LOW BYTE) |
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t XLXH |
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tXLPH |
tPLXH |
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XTAL1 |
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BS1 |
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PAGEL |
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DATA |
ADDR0 (Low Byte) |
DATA (Low Byte) |
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DATA (High Byte) |
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ADDR1 (Low Byte) |
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XA0 |
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XA1 |
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Note: |
The timing requirements shown in Figure 140 (i.e. tDVXH, tXHXL, and tXLDX) also apply to |
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loading operation. |
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Figure 142. Parallel Programming Timing, Reading Sequence (Within the Same Page) with Timing Requirements
LOAD ADDRESS |
READ DATA |
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READ DATA |
LOAD ADDRESS |
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(LOW BYTE) |
(LOW BYTE) |
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(HIGH BYTE) |
(LOW BYTE) |
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tXLOL |
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XTAL1 |
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tBHDV |
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BS1
tOLDV
OE
tOHDZ
DATA |
ADDR0 (Low Byte) |
DATA (Low Byte) |
DATA (High Byte) |
ADDR1 (Low Byte) |
XA0
XA1
Note: The timing requirements shown in Figure 140 (i.e. tDVXH, tXHXL, and tXLDX) also apply to
reading operation. |
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Table 127. |
Parallel Programming Characteristics, VCC = 5 V ± 10% |
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Symbol |
Parameter |
Min |
Typ |
Max |
Units |
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VPP |
Programming Enable Voltage |
11.5 |
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12.5 |
V |
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IPP |
Programming Enable Current |
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250 |
A |
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tDVXH |
Data and Control Valid before XTAL1 High |
67 |
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ns |
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tXLXH |
XTAL1 Low to XTAL1 High |
200 |
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ns |
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tXHXL |
XTAL1 Pulse Width High |
150 |
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ns |
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tXLDX |
Data and Control Hold after XTAL1 Low |
67 |
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ns |
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tXLWL |
XTAL1 Low to |
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Low |
0 |
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ns |
WR |
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291
2467B–09/01