22.4System and Reset Characterizations

Table 22-3.

Reset, Brown-out, and Internal Voltage Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

Power-on Reset Threshold

TA = -40 - 85°C

1.2

V

Voltage (rising)

VPOT

Power-on Reset Threshold

TA = -40 - 85°C

1.1

V

Voltage (falling)(1)

Pin Threshold

VRST

RESET

VCC = 3V

0.2 VCC

0.85 VCC

V

Voltage

tRST

Minimum pulse width on

VCC = 3V

900

ns

RESET

Pin

VHYST

Brown-out Detector

50

mV

Hysteresis

tBOD

Min Pulse Width on Brown-

2

µs

out Reset

VBG

Bandgap reference voltage

VCC = 2.7V,

1.0

1.1

1.2

V

TA = 25°C

tBG

Bandgap reference start-up

VCC = 2.7V,

40

70

µs

time

TA = 25°C

IBG

Bandgap reference current

VCC = 2.7V,

15

µA

consumption

TA = 25°C

Note:

1.

The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)

Table 22-4.

BODLEVEL Fuse Coding(1)

BODLEVEL [2..0] Fuses

Min VBOT

Typ VBOT

Max VBOT

Units

111

BOD Disabled

110

1.8

101

2.7

100

4.3

011

2.3

V

010

2.2

001

1.9

000

2.0

Note:

1.

VBOT may be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to VCC = VBOT during the production test. This guar-

Symbol

Parameter

Condition

Min

Typ

Max

Units

Resolution

Single Ended Conversion

10

Bits

Single Ended Conversion

VREF = 4V, VCC = 4V,

2

LSB

ADC clock = 200 kHz

Single Ended Conversion

VREF = 4V, VCC = 4V,

3

LSB

Absolute accuracy (Including

ADC clock = 1 MHz

Single Ended Conversion

INL, DNL, quantization error,

VREF = 4V, VCC = 4V,

gain and offset error)

1.5

LSB

ADC clock = 200 kHz

Noise Reduction Mode

Single Ended Conversion

VREF = 4V, VCC = 4V,

2.5

LSB

ADC clock = 1 MHz

Noise Reduction Mode

Single Ended Conversion

Integral Non-linearity (INL)

VREF = 4V, VCC = 4V,

1

LSB

ADC clock = 200 kHz

Differential Non-linearity

Single Ended Conversion

VREF = 4V, VCC = 4V,

0.5

LSB

(DNL)

ADC clock = 200 kHz

Single Ended Conversion

Gain Error

VREF = 4V, VCC = 4V,

2.5

LSB

ADC clock = 200 kHz

Single Ended Conversion

Offset Error

VREF = 4V, VCC = 4V,

1.5

LSB

ADC clock = 200 kHz

Conversion Time

Free Running Conversion

13

260

µs

Clock Frequency

50

1000

kHz

VIN

Input Voltage

GND

VREF

V

Input Bandwidth

38.5

kHz

VINT

Internal Voltage Reference

1.0

1.1

1.2

V

RAIN

Analog Input Resistance

100

MΩ

Note: 1.

Values are preliminary.

Symbol

Parameter

Condition

Min

Typ

Max

Units

Resolution

Gain = 1x

10

Bits

Gain = 20x

10

Bits

Gain = 1x

VREF = 4V, VCC = 5V

10

LSB

Absolute Accuracy

ADC clock = 50 - 200 kHz

Gain = 20x

VREF = 4V, VCC = 5V

16

LSB

ADC clock = 50 - 200 kHz

Gain = 1x

Integral Non-Linearity (INL)

VREF = 4V, VCC = 5V

2

LSB

ADC clock = 50 - 200 kHz

(Accuracy after Calibration for Offset and

Gain = 20x

Gain Error)

VREF = 4V, VCC = 5V

4

LSB

ADC clock = 50 - 200 kHz

Gain Error

Gain = 1x

2

%

Gain = 20x

2.5

%

Gain = 1x

VREF = 4V, VCC = 5V

4

LSB

Offset Error

ADC clock = 50 - 200 kHz

Gain = 20x

VREF = 4V, VCC = 5V

6

LSB

ADC clock = 50 - 200 kHz

Clock Frequency

50

200

kHz

Conversion Time

26

65

µs

VREF

Reference Voltage

2.0

AVCC - 0.5

V

VIN

Input Voltage

GND

VCC

V

VDIFF

Input Differential Voltage

0

VREF/Gain

V

ADC Conversion Output

0

1023

LSB

Input Bandwidth

4

kHz

VINT

Internal Voltage Reference

2.4

2.7

2.9

V

RREF

Reference Input Resistance

32

kΩ

RAIN

Analog Input Resistance

100

MΩ

MOSI

tOVSH

tSHOX

tSLSH

SCK

tSHSL

MISO

tSLIV

Figure 22-4. Serial Programming Waveforms

SERIAL DATA INPUT

MSB

LSB

(MOSI)

SERIAL DATA OUTPUT

MSB

LSB

(MISO)

Symbol

Parameter

Min

Typ

Max

Units

1/tCLCL

Oscillator Frequency (ATtiny24/44/84V)

0

4

MHz

tCLCL

Oscillator Period (ATtiny24/44/84V)

250

ns

1/tCLCL

Oscillator Frequency (ATtiny24/44/84, VCC = 4.5V -

0

20

MHz

5.5V)

tCLCL

Oscillator Period (ATtiny24/44/84, VCC = 4.5V - 5.5V)

50

ns

tSHSL

SCK Pulse Width High

2 tCLCL*

ns

tSLSH

SCK Pulse Width Low

2 tCLCL*

ns

tOVSH

MOSI Setup to SCK High

tCLCL

ns

tSHOX

MOSI Hold after SCK High

2 tCLCL

ns

tSLIV

SCK Low to MISO Valid

TBD

TBD

TBD

ns

Note: 1.

2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz