- •1. Pin Configurations
- •1.1 Disclaimer
- •2. Overview
- •2.1 Block Diagram
- •2.2 Pin Descriptions
- •2.2.3 Port B (PB3...PB0)
- •2.2.4 RESET
- •2.2.5 Port A (PA7...PA0)
- •3. Resources
- •4. About Code Examples
- •5. CPU Core
- •5.1 Overview
- •5.2 Architectural Overview
- •5.4 Status Register
- •5.5 General Purpose Register File
- •5.6 Stack Pointer
- •5.7 Instruction Execution Timing
- •5.8 Reset and Interrupt Handling
- •5.8.1 Interrupt Response Time
- •6. Memories
- •6.2 SRAM Data Memory
- •6.2.1 Data Memory Access Times
- •6.3 EEPROM Data Memory
- •6.3.1 EEPROM Read/Write Access
- •6.3.2 Atomic Byte Programming
- •6.3.3 Split Byte Programming
- •6.3.4 Erase
- •6.3.5 Write
- •6.3.6 Preventing EEPROM Corruption
- •6.4 I/O Memory
- •6.4.1 General Purpose I/O Registers
- •6.5 Register Description
- •7. System Clock and Clock Options
- •7.1 Clock Systems and their Distribution
- •7.2 Clock Sources
- •7.3 Default Clock Source
- •7.4 Crystal Oscillator
- •7.6 Calibrated Internal RC Oscillator
- •7.7 External Clock
- •7.8 128 kHz Internal Oscillator
- •7.9 System Clock Prescaler
- •7.9.1 Switching Time
- •7.10 Register Description
- •8. Power Management and Sleep Modes
- •8.1 Sleep Modes
- •8.2 Idle Mode
- •8.3 ADC Noise Reduction Mode
- •8.5 Standby Mode
- •8.6 Power Reduction Register
- •8.7 Minimizing Power Consumption
- •8.7.1 Analog to Digital Converter
- •8.7.2 Analog Comparator
- •8.7.4 Internal Voltage Reference
- •8.7.5 Watchdog Timer
- •8.7.6 Port Pins
- •8.8 Register Description
- •9. System Control and Reset
- •9.0.1 Resetting the AVR
- •9.0.2 Reset Sources
- •9.0.3 Power-on Reset
- •9.0.4 External Reset
- •9.0.6 Watchdog Reset
- •9.1 Internal Voltage Reference
- •9.2 Watchdog Timer
- •9.3 Timed Sequences for Changing the Configuration of the Watchdog Timer
- •9.3.1 Safety Level 1
- •9.3.2 Safety Level 2
- •9.4 Register Description
- •10. Interrupts
- •10.1 Interrupt Vectors
- •11. External Interrupts
- •11.1 Pin Change Interrupt Timing
- •11.2 Register Description
- •12. I/O Ports
- •12.1 Overview
- •12.2 Ports as General Digital I/O
- •12.2.1 Configuring the Pin
- •12.2.2 Toggling the Pin
- •12.2.3 Switching Between Input and Output
- •12.2.4 Reading the Pin Value
- •12.2.5 Digital Input Enable and Sleep Modes
- •12.2.6 Unconnected Pins
- •12.3 Alternate Port Functions
- •12.3.1 Alternate Functions of Port A
- •12.3.2 Alternate Functions of Port B
- •12.4 Register Description
- •13. 8-bit Timer/Counter0 with PWM
- •13.1 Features
- •13.2 Overview
- •13.2.1 Registers
- •13.2.2 Definitions
- •13.3 Timer/Counter Clock Sources
- •13.4 Counter Unit
- •13.5 Output Compare Unit
- •13.5.1 Force Output Compare
- •13.5.2 Compare Match Blocking by TCNT0 Write
- •13.5.3 Using the Output Compare Unit
- •13.6 Compare Match Output Unit
- •13.6.1 Compare Output Mode and Waveform Generation
- •13.7 Modes of Operation
- •13.7.1 Normal Mode
- •13.7.2 Clear Timer on Compare Match (CTC) Mode
- •13.7.3 Fast PWM Mode
- •13.7.4 Phase Correct PWM Mode
- •13.8 Timer/Counter Timing Diagrams
- •13.9 Register Description
- •14. 16-bit Timer/Counter1
- •14.1 Features
- •14.2 Overview
- •14.2.1 Registers
- •14.2.2 Definitions
- •14.2.3 Compatibility
- •14.3.1 Reusing the Temporary High Byte Register
- •14.4 Timer/Counter Clock Sources
- •14.5 Counter Unit
- •14.6 Input Capture Unit
- •14.6.1 Input Capture Trigger Source
- •14.6.2 Noise Canceler
- •14.6.3 Using the Input Capture Unit
- •14.7 Output Compare Units
- •14.7.1 Force Output Compare
- •14.7.2 Compare Match Blocking by TCNT1 Write
- •14.7.3 Using the Output Compare Unit
- •14.8 Compare Match Output Unit
- •14.8.1 Compare Output Mode and Waveform Generation
- •14.9 Modes of Operation
- •14.9.1 Normal Mode
- •14.9.2 Clear Timer on Compare Match (CTC) Mode
- •14.9.3 Fast PWM Mode
- •14.9.4 Phase Correct PWM Mode
- •14.9.5 Phase and Frequency Correct PWM Mode
- •14.10 Timer/Counter Timing Diagrams
- •14.11 Register Description
- •15. Timer/Counter Prescaler
- •15.0.1 Prescaler Reset
- •15.0.2 External Clock Source
- •15.1 Register Description
- •16.1 Features
- •16.2 Overview
- •16.3 Functional Descriptions
- •16.3.2 SPI Master Operation Example
- •16.3.3 SPI Slave Operation Example
- •16.3.5 Start Condition Detector
- •16.3.6 Clock speed considerations
- •16.4 Alternative USI Usage
- •16.4.4 Edge Triggered External Interrupt
- •16.4.5 Software Interrupt
- •16.5 Register Descriptions
- •17. Analog Comparator
- •17.1 Analog Comparator Multiplexed Input
- •17.2 Register Description
- •18. Analog to Digital Converter
- •18.1 Features
- •18.2 Overview
- •18.3 ADC Operation
- •18.4 Starting a Conversion
- •18.5 Prescaling and Conversion Timing
- •18.6 Changing Channel or Reference Selection
- •18.6.1 ADC Input Channels
- •18.6.2 ADC Voltage Reference
- •18.7 ADC Noise Canceler
- •18.7.1 Analog Input Circuitry
- •18.7.2 Analog Noise Canceling Techniques
- •18.7.3 ADC Accuracy Definitions
- •18.8 ADC Conversion Result
- •18.8.1 Single Ended Conversion
- •18.8.2 Unipolar Differential Conversion
- •18.8.3 Bipolar Differential Conversion
- •18.9 Temperature Measurement
- •18.10 Register Description
- •18.10.3.1 ADLAR = 0
- •18.10.3.2 ADLAR = 1
- •19. debugWIRE On-chip Debug System
- •19.1 Features
- •19.2 Overview
- •19.3 Physical Interface
- •19.4 Software Break Points
- •19.5 Limitations of debugWIRE
- •19.6 Register Description
- •20. Self-Programming the Flash
- •20.0.1 Performing Page Erase by SPM
- •20.0.2 Filling the Temporary Buffer (Page Loading)
- •20.0.3 Performing a Page Write
- •20.1.1 EEPROM Write Prevents Writing to SPMCSR
- •20.1.2 Reading the Fuse and Lock Bits from Software
- •20.1.3 Preventing Flash Corruption
- •20.1.4 Programming Time for Flash when Using SPM
- •20.2 Register Description
- •21. Memory Programming
- •21.1 Program And Data Memory Lock Bits
- •21.2 Fuse Bytes
- •21.2.1 Latching of Fuses
- •21.3 Signature Bytes
- •21.4 Calibration Byte
- •21.5 Page Size
- •21.6 Serial Downloading
- •21.6.1 Serial Programming Algorithm
- •21.6.2 Serial Programming Instruction set
- •21.7 High-voltage Serial Programming
- •21.8.2 Considerations for Efficient Programming
- •21.8.3 Chip Erase
- •21.8.4 Programming the Flash
- •21.8.5 Programming the EEPROM
- •21.8.6 Reading the Flash
- •21.8.7 Reading the EEPROM
- •21.8.8 Programming and Reading the Fuse and Lock Bits
- •21.8.9 Reading the Signature Bytes and Calibration Byte
- •22. Electrical Characteristics
- •22.1 Absolute Maximum Ratings*
- •22.2 Speed Grades
- •22.3 Clock Characterizations
- •22.3.1 Calibrated Internal RC Oscillator Accuracy
- •22.3.2 External Clock Drive Waveforms
- •22.3.3 External Clock Drive
- •22.4 System and Reset Characterizations
- •22.6 Serial Programming Characteristics
- •22.7 High-voltage Serial Programming Characteristics
- •23.1 Active Supply Current
- •23.2 Idle Supply Current
- •23.3 Supply Current of IO modules
- •23.3.0.1 Example 1
- •23.5 Standby Supply Current
- •23.7 Pin Driver Strength
- •23.8 Pin Threshold and Hysteresis
- •23.9 BOD Threshold and Analog Comparator Offset
- •23.10 Internal Oscillator Speed
- •23.11 Current Consumption of Peripheral Units
- •23.12 Current Consumption in Reset and Reset Pulsewidth
- •24. Register Summary
- •25. Instruction Set Summary
- •26. Ordering Information
- •26.1 ATtiny24
- •26.2 ATtiny44
- •26.3 ATtiny84
- •27. Packaging Information
- •28. Errata
- •28.1 ATtiny24
- •28.2 ATtiny44
- •28.3 ATtiny84
- •29. Datasheet Revision History
ATtiny24/44/84
Figure 18-12. Differential Non-linearity (DNL)
Output Code
0x3FF
|
1 LSB |
|
DNL |
0x000 |
|
0 |
VREF Input Voltage |
•Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
•Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB.
18.8ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). The form of the conversion result depends on the type of the conversio as there are three types of conversions: single ended conversion, unipolar differential conversion and bipolar differential conversion.
18.8.1Single Ended Conversion
For single ended conversion, the result is
ADC VIN 1024
= --------------------------
VREF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 18-3 on page 151 and Table 18-4 on page 152). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. The result is presented in onesided form, from 0x3FF to 0x000.
18.8.2Unipolar Differential Conversion
If differential channels and an unipolar input mode are used, the result is
ADC (VPOS – VNEG) 1024 GAIN
= -------------------------------------------------------
VREF
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference. The voltage of the positive pin must always be larger
149
8006E–AVR–09/06