when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. Figure 14-4 shows a block diagram of the Output Compare unit.

Figure 14-4. Output Compare Unit, Block Diagram

DATA BUS

= (8/16-bit Comparator )

OCFnx (Int.Req.)

14.7.1Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0H/L Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A/B to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled.

14.7.2Using the Output Compare Unit

Since writing TCNT0H/L will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0H/L when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0H/L equals the OCR0A/B value, the Compare Match will be missed.

14.8Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 14-5 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value.

Figure 14-5. Timer/Counter Timing Diagram, no Prescaling

clkI/O

clkTn

(clkI/O/1)

TOVn

Figure 14-6 shows the same timing data, but with the prescaler enabled.

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Figure 14-6. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

clkI/O

clkTn

(clkI/O/8)

TOVn

Figure 14-7 shows the setting of OCF0A and OCF0B in Normal mode.

Figure 14-7. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)

shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 14-8. Timer/Counter Timing Diagram, CTC mode, with Prescaler (fclk_I/O/8)

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14.9Accessing Registers in 16-bit Mode

In 16-bit mode (the TCW0 bit is set to one) the TCNT0H/L and OCR0A/B or TCNT0L/H and OCR0B/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. The 16-bit Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read.

There is one exception in the temporary register usage. In the Output Compare mode the 16-bit Output Compare Register OCR0A/B is read without the temporary register, because the Output Compare Register contains a fixed value that is only changed by CPU access. However, in 16bit Input Capture mode the ICR0 register formed by the OCR0A and OCR0B registers must be accessed with the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte.

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The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B registers.

Assembly Code Example

...

; Set TCNT0 to 0x01FF ldi r17,0x01

ldi r16,0xFF out TCNT0H,r17 out TCNT0L,r16

; Read TCNT0 into r17:r16 in r16,TCNT0L

in r17,TCNT0H

...

C Code Example

unsigned int i;

...

/* Set TCNT0 to 0x01FF */ TCNT0H = 0x01;

TCNT0L = 0xff;

/* Read TCNT0 into i */ i = TCNT0L;

i |= ((unsigned int)TCNT0H << 8);

...

Note: 1. The example code assumes that the part specific header file is included.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT0H/L value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access.

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The following code examples show how to do an atomic read of the TCNT0 register contents.

Reading any of the OCR0 register can be done by using the same principle.

Assembly Code Example

TIM0_ReadTCNT0:

; Save global interrupt flag in r18,SREG

; Disable interrupts cli

; Read TCNT0 into r17:r16 in r16,TCNT0L

in r17,TCNT0H

; Restore global interrupt flag out SREG,r18

ret

C Code Example

unsigned int TIM0_ReadTCNT0( void )

{

unsigned char sreg; unsigned int i;

/* Save global interrupt flag */ sreg = SREG;

/* Disable interrupts */ _CLI();

/* Read TCNT0 into i */ i = TCNT0L;

i |= ((unsigned int)TCNT0H << 8); /* Restore global interrupt flag */ SREG = sreg;

return i;

}

Note: 1. The example code assumes that the part specific header file is included.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT0H/L value in the r17:r16 register pair.

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