ATmega48/88/168

27.7.14Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 293 for details on Command and Address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low Byte, 0x00.

3.Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4.Set OE to “1”.

27.7.15Parallel Programming Characteristics

For characteristics of the parallel programming, see “Parallel Programming Characteristics” on page 313.

27.8Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 27-15 on page 300, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.

Figure 27-7. Serial Programming and Verify(1)

+1.8 - 5.5V

VCC

+1.8 - 5.5V(2)

MOSI

AVCC

MISO

SCK

XTAL1

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.

2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

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27.8.1Serial Programming Pin Mapping

Table 27-15. Pin Mapping Serial Programming

27.8.2Serial Programming Algorithm

When writing serial data to the ATmega48/88/168, data is clocked on the rising edge of SCK.

When reading data from the ATmega48/88/168, data is clocked on the falling edge of SCK. See

Figure 27-9 for timing details.

To program and verify the ATmega48/88/168 in the serial programming mode, the following sequence is recommended (See Serial Programming Instruction set in Table 27-17 on page 301):

1.Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.

2.Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI.

3.The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.

4.The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of

the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page (See Table 27-16). Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming.

5.A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the

user must wait at least tWD_EEPROM before issuing the next byte (See Table 27-16). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.

B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is

not used, the used must wait at least tWD_EEPROM before issuing the next byte (See Table 27-16). In a chip erased device, no 0xFF in the data file(s) need to be programmed.

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6.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.

7.At the end of the programming session, RESET can be set high to commence normal operation.

8.Power-off sequence (if needed): Set RESET to “1”.

Turn VCC power off.

Table 27-16. Typical Wait Delay Before Writing the Next Flash or EEPROM Location

27.8.3Serial Programming Instruction set

Table 27-17 on page 301 and Figure 27-8 on page 302 describes the Instruction set.

Table 27-17. Serial Programming Instruction Set (Hexadecimal values)

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Table 27-17. Serial Programming Instruction Set (Hexadecimal values) (Continued)

Notes: 1. Not all instructions are applicable for all parts.

2.a = address.

3.Bits are programmed ‘0’, unprogrammed ‘1’.

4.To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .

5.Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.

6.Instructions accessing program memory use a word address. This word may be random within the page range.

7.See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out.

Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 27-8 on page 302.

Figure 27-8. Serial Programming Instruction example

Serial Programming Instruction

Page Buffer

Page Offset

Page 0

Page 1

Page 2

Page Number

Page N-1

Program Memory/

EEPROM Memory

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