Serial Downloading

Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.

2.tWLRH_CE is valid for the Chip Erase command.

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 75 on page 163, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.

Figure 78. Serial Programming and Verify(1)

+1.8 - 5.5V

VCC

MOSI

MISO

SCK

XTAL1

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.

2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

Serial Programming

Algorithm

2543H–AVR–02/05

ATtiny2313/V

When writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK.

When reading data from the ATtiny2313, data is clocked on the falling edge of SCK. See Figure 79, Figure 80 and Table 79 for timing details.

To program and verify the ATtiny2313 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 78 on page 174):

1.Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.

2.Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI.

3.The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.

4.The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 4 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 6 MSB of the address. If polling (RDY/BSY) is

not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 77 on page 174.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming.

5.A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling

(RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 77 on page 174.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed.

B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 5 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used

must wait at least tWD_EEPROM before issuing the next page (See Table 77 on page 174). In a chip erased device, no 0xFF in the data file(s) need to be

programmed.

6.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.

7.At the end of the programming session, RESET can be set high to commence normal operation.

8.Power-off sequence (if needed): Set RESET to “1”.

Turn VCC power off.

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