
- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •General Purpose I/O Registers
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port D
- •Register Description for I/O-Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Overview
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04
- •Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04
- •Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04
- •Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03
- •Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03
- •Table of Contents

Table 68. Fuse Low Byte
Fuse Low Byte |
Bit No |
Description |
Default Value |
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CKDIV8 |
7 |
Divide clock by 8 |
0 |
(programmed) |
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CKOUT |
6 |
Output Clock on CKOUT pin |
1 |
(unprogrammed) |
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SUT1 |
5 |
Select start-up time |
1 |
(unprogrammed)(1) |
SUT0 |
4 |
Select start-up time |
0 |
(programmed)(1) |
CKSEL3 |
3 |
Select Clock source |
0 |
(programmed)(2) |
CKSEL2 |
2 |
Select Clock source |
1 |
(unprogrammed)(2) |
CKSEL1 |
1 |
Select Clock source |
0 |
(programmed)(2) |
CKSEL0 |
0 |
Select Clock source |
0 |
(programmed)(2) |
Note: 1. The default value of SUT1..0 results in maximum start-up time for the default clock
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source. See Table 15 on page 33 for details. |
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2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. |
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The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are |
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locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the |
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Lock bits. |
Latching of Fuses |
The fuse values are latched when the device enters programming mode and changes of |
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the fuse values will have no effect until the part leaves Programming mode. This does |
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not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses |
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are also latched on Power-up in Normal mode. |
Signature Bytes
Calibration Byte
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space.
For the ATtiny2313 the signature bytes are:
1.0x000: 0x1E (indicates manufactured by Atmel).
2.0x001: 0x91 (indicates 2KB Flash memory).
3.0x002: 0x0A (indicates ATtiny2313 device when 0x001 is 0x91).
The ATtiny2313 stores two different calibration values for the internal RC Oscillator. These bytes resides in the high byte of address 0x0000 and 0x0001 in the signature address space for 4 and 8 MHz respectively. During reset, the 4 MHz value is automatically written to the “Oscillator Calibration Register – OSCCAL” on page 25, to ensure correct frequency of the calibrated RC Oscillator.
Page Size
Table 69. No. of Words in a Page and No. of Pages in the Flash
Flash Size |
Page Size |
PCWORD |
No. of Pages |
PCPAGE |
PCMSB |
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1K words (2K bytes) |
16 words |
PC[3:0] |
64 |
PC[9:4] |
9 |
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160 ATtiny2313/V
2543H–AVR–02/05

Parallel Programming
Parameters, Pin
Mapping, and
Commands
Signal Names
ATtiny2313/V
Table 70. No. of Words in a Page and No. of Pages in the EEPROM
EEPROM Size |
Page Size |
PCWORD |
No. of Pages |
PCPAGE |
EEAMSB |
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128 bytes |
4 bytes |
EEA[1:0] |
32 |
EEA[6:2] |
6 |
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This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny2313. Pulses are assumed to be at least 250 ns unless otherwise noted.
In this section, some pins of the ATtiny2313 are referenced by signal names describing their functionality during parallel programming, see Figure 69 and Table 71. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 73.
When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 74.
Figure 69. Parallel Programming
+5V
RDY/BSY PD1
VCC
OE PD2
WR PD3
BS1/PAGEL PD4
XA0 |
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PD5 |
PB7 - PB0 |
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DATA I/O |
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XA1/BS2 |
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PD6 |
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+12 V RESET
XTAL1
GND
Table 71. Pin Name Mapping
Signal Name |
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in |
Pin |
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Programming |
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Mode |
Name |
I/O |
Function |
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PD1 |
O |
0: Device is busy programming, 1: Device is ready for |
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RDY/BSY |
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new command. |
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PD2 |
I |
Output Enable (Active low). |
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OE |
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PD3 |
I |
Write Pulse (Active low). |
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WR |
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Byte Select 1 (“0” selects low byte, “1” selects high |
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BS1/PAGEL |
PD4 |
I |
byte). |
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Program Memory and EEPROM Data Page Load. |
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161
2543H–AVR–02/05

Table 71. Pin Name Mapping (Continued)
Signal Name |
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in |
Pin |
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Programming |
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Mode |
Name |
I/O |
Function |
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XA0 |
PD5 |
I |
XTAL Action Bit 0 |
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XTAL Action Bit 1. |
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XA1/BS2 |
PD6 |
I |
Byte Select 2 (“0” selects low byte, “1” selects 2’nd high |
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byte). |
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DATA I/O |
PB7-0 |
I/O |
Bi-directional Data bus (Output when |
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is low). |
OE |
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Table 72. Pin Values Used to Enter Programming Mode
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Pin |
Symbol |
Value |
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XA1 |
Prog_enable[3] |
0 |
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XA0 |
Prog_enable[2] |
0 |
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BS1 |
Prog_enable[1] |
0 |
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Prog_enable[0] |
0 |
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WR |
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Table 73. XA1 and XA0 Coding
XA1 |
XA0 |
Action when XTAL1 is Pulsed |
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0 |
0 |
Load Flash or EEPROM Address (High or low address byte |
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determined by BS1). |
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0 |
1 |
Load Data (High or Low data byte for Flash determined by BS1). |
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1 |
0 |
Load Command |
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1 |
1 |
No Action, Idle |
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Table 74. Command Byte Bit Coding
Command Byte |
Command Executed |
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1000 0000 |
Chip Erase |
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0100 0000 |
Write Fuse bits |
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0010 0000 |
Write Lock bits |
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0001 0000 |
Write Flash |
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0001 0001 |
Write EEPROM |
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0000 1000 |
Read Signature Bytes and Calibration byte |
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0000 0100 |
Read Fuse and Lock bits |
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0000 0010 |
Read Flash |
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0000 0011 |
Read EEPROM |
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162 ATtiny2313/V
2543H–AVR–02/05