- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •General Purpose I/O Registers
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port D
- •Register Description for I/O-Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Overview
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04
- •Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04
- •Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04
- •Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03
- •Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03
- •Table of Contents
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ATtiny2313/V |
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Pin Descriptions |
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VCC |
Digital supply voltage. |
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GND |
Ground. |
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Port A (PA2..PA0) |
Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each |
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bit). The Port A output buffers have symmetrical drive characteristics with both high sink |
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and source capability. As inputs, Port A pins that are externally pulled low will source |
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current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset |
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condition becomes active, even if the clock is not running. |
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Port A also serves the functions of various special features of the ATtiny2313 as listed |
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on page 52. |
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Port B (PB7..PB0) |
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each |
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bit). The Port B output buffers have symmetrical drive characteristics with both high sink |
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and source capability. As inputs, Port B pins that are externally pulled low will source |
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current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset |
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condition becomes active, even if the clock is not running. |
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Port B also serves the functions of various special features of the ATtiny2313 as listed |
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on page 52. |
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Port D (PD6..PD0) |
Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each |
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bit). The Port D output buffers have symmetrical drive characteristics with both high sink |
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and source capability. As inputs, Port D pins that are externally pulled low will source |
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current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset |
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condition becomes active, even if the clock is not running. |
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Port D also serves the functions of various special features of the ATtiny2313 as listed |
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on page 55. |
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Reset input. A low level on this pin for longer than the minimum pulse length will gener- |
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RESET |
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ate a reset, even if the clock is not running. The minimum pulse length is given in Table |
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15 on page 33. Shorter pulses are not guaranteed to generate a reset. The Reset Input |
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is an alternate function for PA2 and dW. |
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XTAL1 |
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. |
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XTAL1 is an alternate function for PA0. |
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XTAL2 |
Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1. |
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About Code |
This documentation contains simple code examples that briefly show how to use various |
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Examples |
parts of the device. These code examples assume that the part specific header file is |
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included before compilation. Be aware that not all C compiler vendors include bit defini- |
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tions in the header files and interrupt handling in C is compiler dependent. Please |
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confirm with the C compiler documentation for more details. |
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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2543H–AVR–02/05