		ATmega128
Table of Contents	Features................................................................................................	1
	Pin Configurations...............................................................................	2
	Overview...............................................................................................	2
	Block Diagram ......................................................................................................	3
	ATmega103 and ATmega128 Compatibility .........................................................	4
	Pin Descriptions....................................................................................................	5
	About Code Examples.........................................................................	7
	AVR CPU Core .....................................................................................	8
	Introduction ...........................................................................................................	8
	Architectural Overview..........................................................................................	8
	ALU – Arithmetic Logic Unit..................................................................................	9
	Status Register .....................................................................................................	9
	General Purpose Register File ...........................................................................	10
	Stack Pointer ......................................................................................................	12
	Instruction Execution Timing...............................................................................	13
	Reset and Interrupt Handling..............................................................................	13
	AVR ATmega128 Memories ..............................................................	16
	In-System Reprogrammable Flash Program Memory ........................................	16
	SRAM Data Memory...........................................................................................	17
	EEPROM Data Memory......................................................................................	19
	I/O Memory .........................................................................................................	24
	External Memory Interface..................................................................................	24
	System Clock and Clock Options ....................................................	34
	Clock Systems and their Distribution ..................................................................	34
	Clock Sources.....................................................................................................	35
	Default Clock Source ..........................................................................................	35
	Crystal Oscillator.................................................................................................	36
	Low-frequency Crystal Oscillator ........................................................................	37
	External RC Oscillator ........................................................................................	38
	Calibrated Internal RC Oscillator ........................................................................	39
	External Clock.....................................................................................................	40
	Timer/Counter Oscillator.....................................................................................	41
	Power Management and Sleep Modes.............................................	42
	Idle Mode ............................................................................................................	43
	ADC Noise Reduction Mode...............................................................................	43
	Power-down Mode..............................................................................................	43
	Power-save Mode...............................................................................................	43
	Standby Mode.....................................................................................................	44
	Extended Standby Mode ....................................................................................	44
		i
2467K–AVR–04/04

Minimizing Power Consumption .........................................................................	45
System Control and Reset ................................................................	47
Internal Voltage Reference .................................................................................	52
Watchdog Timer .................................................................................................	52
Timed Sequences for Changing the Configuration of the Watchdog Timer .......	55
Interrupts ............................................................................................	57
Interrupt Vectors in ATmega128.........................................................................	57
I/O Ports..............................................................................................	63
Introduction .........................................................................................................	63
Ports as General Digital I/O ................................................................................	64
Alternate Port Functions .....................................................................................	68
Register Description for I/O Ports .......................................................................	84
External Interrupts.............................................................................	87
8-bit Timer/Counter0 with PWM and Asynchronous Operation ....	90
Overview.............................................................................................................	90
Timer/Counter Clock Sources.............................................................................	91
Counter Unit........................................................................................................	91
Output Compare Unit..........................................................................................	92
Compare Match Output Unit ...............................................................................	94
Modes of Operation ............................................................................................	95
Timer/Counter Timing Diagrams.........................................................................	99
8-bit Timer/Counter Register Description .........................................................	101
Asynchronous Operation of the Timer/Counter ................................................	104
Timer/Counter Prescaler...................................................................................	107
16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3).......	109
Overview...........................................................................................................	109
Accessing 16-bit Registers ...............................................................................	112
Timer/Counter Clock Sources...........................................................................	115
Counter Unit......................................................................................................	115
Input Capture Unit.............................................................................................	116
Output Compare Units ......................................................................................	118
Compare Match Output Unit .............................................................................	120
Modes of Operation ..........................................................................................	121
Timer/Counter Timing Diagrams.......................................................................	128
16-bit Timer/Counter Register Description .......................................................	131

Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers ...

143

8-bit Timer/Counter2 with PWM......................................................

145

ii ATmega128

2467K–AVR–04/04

ATmega128

Overview...........................................................................................................	145
Timer/Counter Clock Sources...........................................................................	146
Counter Unit......................................................................................................	146
Output Compare Unit........................................................................................	147
Compare Match Output Unit .............................................................................	149
Modes of Operation ..........................................................................................	150
Timer/Counter Timing Diagrams.......................................................................	155
8-bit Timer/Counter Register Description .....................................	157
Output Compare Modulator (OCM1C2)..........................................	161
Overview...........................................................................................................	161
Description........................................................................................................	161
Serial Peripheral Interface – SPI.....................................................	163
SS Pin Functionality..........................................................................................	167
Data Modes ......................................................................................................	170
USART ..............................................................................................	171
Overview...........................................................................................................	171
Clock Generation ..............................................................................................	173
Frame Formats .................................................................................................	176
USART Initialization..........................................................................................	177
Data Transmission – The USART Transmitter .................................................	178
Data Reception – The USART Receiver ..........................................................	181
Asynchronous Data Reception .........................................................................	185
Multi-processor Communication Mode .............................................................	188
USART Register Description ............................................................................	190
Examples of Baud Rate Setting........................................................................	195
Two-wire Serial Interface ................................................................	199
Features............................................................................................................	199
Two-wire Serial Interface Bus Definition...........................................................	199
Data Transfer and Frame Format .....................................................................	200
Multi-master Bus Systems, Arbitration and Synchronization ............................	202
Overview of the TWI Module ............................................................................	205
TWI Register Description..................................................................................	207
Using the TWI ...................................................................................................	209
Transmission Modes.........................................................................................	214
Multi-master Systems and Arbitration...............................................................	227
Analog Comparator .........................................................................	229
Analog Comparator Multiplexed Input ..............................................................	230
Analog to Digital Converter ............................................................	232

iii

2467K–AVR–04/04

Features............................................................................................................	232
Operation ..........................................................................................................	234
Starting a Conversion .......................................................................................	234
Prescaling and Conversion Timing ...................................................................	235
Changing Channel or Reference Selection ......................................................	237
ADC Noise Canceler.........................................................................................	238
ADC Conversion Result....................................................................................	243
JTAG Interface and On-chip Debug System .................................	249
Features............................................................................................................	249
Overview...........................................................................................................	249
Test Access Port – TAP....................................................................................	249
TAP Controller ..................................................................................................	251
Using the Boundary-scan Chain .......................................................................	252
Using the On-chip Debug System ....................................................................	252
On-chip Debug Specific JTAG Instructions ......................................................	253
On-chip Debug Related Register in I/O Memory ..............................................	254
Using the JTAG Programming Capabilities ......................................................	254
Bibliography ......................................................................................................	254
IEEE 1149.1 (JTAG) Boundary-scan................................................................	255
Features............................................................................................................	255
System Overview..............................................................................................	255
Data Registers ..................................................................................................	255
Boundary-scan Specific JTAG Instructions ......................................................	257
Boundary-scan Related Register in I/O Memory ..............................................	258
Boundary-scan Chain .......................................................................................	259
ATmega128 Boundary-scan Order...................................................................	269
Boundary-scan Description Language Files .....................................................	275
Boot Loader Support – Read-While-Write Self-Programming.....	276
Boot Loader Features .......................................................................................	276
Application and Boot Loader Flash Sections ....................................................	276
Read-While-Write and No Read-While-Write Flash Sections...........................	276
Boot Loader Lock Bits.......................................................................................	278
Entering the Boot Loader Program ...................................................................	279
Addressing the Flash During Self-Programming ..............................................	281
Self-Programming the Flash .............................................................................	282
Memory Programming.....................................................................	289
Program and Data Memory Lock Bits...............................................................	289
Fuse Bits...........................................................................................................	290
Signature Bytes ................................................................................................	292
Calibration Byte ................................................................................................	292
Parallel Programming Parameters, Pin Mapping, and Commands ..................	293
Parallel Programming .......................................................................................	295
Serial Downloading...........................................................................................	304

iv ATmega128

2467K–AVR–04/04

ATmega128

SPI Serial Programming Pin Mapping ..............................................................	304
Programming Via the JTAG Interface...............................................................	309
Electrical Characteristics................................................................	322
Absolute Maximum Ratings*.............................................................................	322
DC Characteristics............................................................................................	322
External Clock Drive Waveforms ......................................................................	324
External Clock Drive .........................................................................................	324
Two-wire Serial Interface Characteristics .........................................................	325
SPI Timing Characteristics ...............................................................................	326
ADC Characteristics – Preliminary Data...........................................................	328
External Data Memory Timing ..........................................................................	329
ATmega128 Typical Characteristics – Preliminary Data..............	334
Register Summary ...........................................................................	356
Instruction Set Summary ................................................................	359
Ordering Information.......................................................................	362
Packaging Information ....................................................................	363
64A ...................................................................................................................	363
64M1.................................................................................................................	364
Errata ................................................................................................	365
ATmega128 Rev. I............................................................................................	365
ATmega128 Rev. H ..........................................................................................	366
ATmega128 Rev. G ..........................................................................................	367
ATmega128 Rev. F...........................................................................................	369
Datasheet Change Log for ATmega128.........................................	371
Changes from Rev. 2467J-12/03 to Rev.
2467K-03/04 .....................................................................................................	371
Changes from Rev. 2467I-09/03 to Rev.
2467J-12/03......................................................................................................	371
Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03 ....................................	371
Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03...................................	371
Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02 ...................................	372
Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02 ...................................	372
Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02 ...................................	372
Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02...................................	373
Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02 ...................................	373
Table of Contents .................................................................................	i

2467K–AVR–04/04

vi ATmega128

2467K–AVR–04/04

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