- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Register Description for I/O Ports
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •Port E Data Register – PORTE
- •Port F Data Register – PORTF
- •Port G Data Register – PORTG
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Section – BLS
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics – Preliminary Data
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. I
- •ATmega128 Rev. H
- •ATmega128 Rev. G
- •ATmega128 Rev. F
- •Datasheet Change Log for ATmega128
- •Changes from Rev. 2467J-12/03 to Rev. 2467K-03/04
- •Changes from Rev. 2467I-09/03 to Rev. 2467J-12/03
- •Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03
- •Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03
- •Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02
- •Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02
- •Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02
- •Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02
- •Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02
- •Table of Contents
Ordering Information
Speed (MHz) |
Power Supply |
Ordering Code |
Package |
Operation Range |
|
|
|
|
|
8 |
2.7 - 5.5V |
ATmega128L-8AC |
64A |
Commercial |
|
|
ATmega128L-8MC |
64M1 |
(0oC to 70oC) |
|
|
|
|
|
|
|
ATmega128L-8AI |
64A |
Industrial |
|
|
ATmega128L-8MI |
64M1 |
(-40oC to 85oC) |
|
|
|
|
|
16 |
4.5 - 5.5V |
ATmega128-16AC |
64A |
Commercial |
|
|
ATmega128-16MC |
64M1 |
(0oC to 70oC) |
|
|
|
|
|
|
|
ATmega128-16AI |
64A |
Industrial |
|
|
ATmega128-16MI |
64M1 |
(-40oC to 85oC) |
|
|
|
|
|
Note: 1. The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
|
Package Type |
|
|
64A |
64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) |
|
|
64M1 |
64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (MLF) |
|
|
362 ATmega128
2467K–AVR–04/04
ATmega128
Packaging Information
64A
PIN 1 
B
PIN 1 IDENTIFIER
e |
E1 E |
D1
D
C |
0˚~7˚ |
A1 A2
L
Notes: 1. This package conforms to JEDEC reference MS-026, Variation AEB.
2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.
3.Lead coplanarity is 0.10 mm maximum.
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL |
MIN |
NOM |
MAX |
NOTE |
A |
– |
– |
1.20 |
|
|
|
|
|
|
A1 |
0.05 |
– |
0.15 |
|
A2 |
0.95 |
1.00 |
1.05 |
|
|
|
|
|
|
D |
15.75 |
16.00 |
16.25 |
|
|
|
|
|
|
D1 |
13.90 |
14.00 |
14.10 |
Note 2 |
|
|
|
|
|
E |
15.75 |
16.00 |
16.25 |
|
E1 |
13.90 |
14.00 |
14.10 |
Note 2 |
|
|
|
|
|
B |
0.30 |
– |
0.45 |
|
|
|
|
|
|
C |
0.09 |
– |
0.20 |
|
|
|
|
|
|
L |
0.45 |
– |
0.75 |
|
|
|
|
|
|
e |
|
0.80 TYP |
|
|
|
|
|
|
|
10/5/2001
2325 Orchard Parkway |
TITLE |
DRAWING NO. |
REV. |
|
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, |
|
|
||
R San Jose, CA 95131 |
64A |
B |
||
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) |
||||
|
|
|
363
2467K–AVR–04/04
64M1
D
Marked Pin# 1 ID
E
|
|
C SEATING PLANE |
|
TOP VIEW |
|
A1 |
|
|
|
|
|
|
|
A |
|
|
|
0.08 |
C |
L |
Pin #1 Corner |
SIDE VIEW |
|
D2 |
|
||
|
|
|
|
|
1 |
|
|
2
|
|
3 |
COMMON DIMENSIONS |
||
|
|
|
|||
|
|
|
(Unit of Measure = mm) |
||
E2 |
|
SYMBOL |
MIN |
NOM |
MAX NOTE |
|
|
A |
0.80 |
0.90 |
1.00 |
|
|
A1 |
– |
0.02 |
0.05 |
|
|
b |
0.23 |
0.25 |
0.28 |
|
|
D |
|
9.00 BSC |
|
|
|
D2 |
5.20 |
5.40 |
5.60 |
b |
e |
E |
|
9.00 BSC |
|
|
|
|
|
||
|
|
E2 |
5.20 |
5.40 |
5.60 |
BOTTOM VIEW |
|
e |
|
0.50 BSC |
|
|
|
|
|
||
|
|
L |
0.35 |
0.40 |
0.45 |
Notes: 1. JEDEC Standard MO-220, Fig. 1, VMMD.
01/15/03
TITLE
|
2325 Orchard Parkway |
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm |
|
San Jose, CA 95131 |
|
R |
Micro Lead Frame Package (MLF) |
DRAWING NO. REV.
64M1 C
364 ATmega128
2467K–AVR–04/04