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Рыбницкий Филиал Приднестровского Государственного Университета им.Т.Г.Шевченко

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AVR / datasheets / atmega_128.pdf

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Electrical Characteristics

Note: Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

Absolute Maximum Ratings*

..................................Operating Temperature				-55°C to +125°C	*NOTICE: Stresses beyond those listed under “Absolute
					Maximum Ratings” may cause permanent dam-
Storage Temperature .....................................				-65°C to +150°C	age to the device. This is a stress rating only and
					functional operation of the device at these or
Voltage on any Pin except			RESET		other conditions beyond those indicated in the
with respect to Ground ................................				- 1.0V to VCC+0.5V	operational sections of this specification is not
Voltage on		with respect to Ground		-1.0V to +13.0V	implied. Exposure to absolute maximum rating
Voltage on	RESET	with respect to Ground		-1.0V to +13.0V	conditions for extended periods may affect device
Maximum Operating Voltage				6.0V	reliability.
Maximum Operating Voltage				6.0V
DC Current per I/O Pin ...............................................				40.0 mA
DC Current VCC and GND Pins................................				200.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)

Symbol	Parameter		Condition					Min	Typ	Max	Units

VIL	Input Low Voltage		Except XTAL1 and							(1)	V
						pins		-0.5		0.2 VCC
			RESET			pins		-0.5		0.2 VCC
VIL1	Input Low Voltage		XTAL1 pin, External							(1)	V
VIL1	Input Low Voltage		Clock Selected					-0.5		0.1 VCC	V
										(1)
VIL2	Input Low Voltage	RESET pin						-0.5		(1)	V
VIL2	Input Low Voltage	RESET pin						-0.5		0.2 VCC	V
VIH	Input High Voltage		Except XTAL1 and					(2)		VCC + 0.5	V
						pins		0.6 VCC
			RESET			pins		0.6 VCC
VIH1			XTAL1 pin, External					(2)
VIH1	Input High Voltage		Clock Selected					0.7 VCC		VCC + 0.5	V
								(2)
VIH2	Input High Voltage	RESET pin						(2)		VCC + 0.5	V
VIH2	Input High Voltage	RESET pin						0.85 VCC		VCC + 0.5	V
	Output Low Voltage(3)		I	OL	= 20 mA, V		= 5V			0.7	V
VOL				OL			CC
VOL	(Ports A,B,C,D, E, F, G)		IOL = 10 mA, VCC = 3V							0.5	V
	(Ports A,B,C,D, E, F, G)		IOL = 10 mA, VCC = 3V							0.5	V
VOH	Output High Voltage(4)		IOH = -20 mA, VCC = 5V					4.0			V
VOH	(Ports A,B,C,D)		IOH = -10 mA, VCC = 3V					2.2			V
	(Ports A,B,C,D)		IOH = -10 mA, VCC = 3V					2.2			V
IIL	Input Leakage		Vcc = 5.5V, pin low							8.0	µA
IIL	Current I/O Pin		(absolute value)							8.0	µA
IIH	Input Leakage		Vcc = 5.5V, pin high							8.0	µA
IIH	Current I/O Pin		(absolute value)							8.0	µA
RRST	Reset Pull-up Resistor							30		100	kΩ
RPEN	PEN Pull-up Resistor							25		100	kΩ
RPU	I/O Pin Pull-up Resistor							20		100	kΩ

322 ATmega128

2467K–AVR–04/04

ATmega128

TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)			(Continued)
Symbol	Parameter	Condition	Min	Typ	Max	Units

		Active 4 MHz, VCC = 3V			5	mA
		(ATmega128L)			5	mA
		(ATmega128L)

		Active 8 MHz, VCC = 5V			20	mA
		(ATmega128)			20	mA
	Power Supply Current	(ATmega128)

ICC		Idle 4 MHz, VCC = 3V			2	mA
		Idle 4 MHz, VCC = 3V
		(ATmega128L)
		(ATmega128L)
		Idle 8 MHz, VCC = 5V			12	mA
		(ATmega128)			12	mA
		(ATmega128)

	Power-down mode(5)	WDT enabled, VCC = 3V		< 25	40	µA
	Power-down mode(5)	WDT disabled, VCC = 3V		< 10	25	µA
		WDT disabled, VCC = 3V		< 10	25	µA
VACIO	Analog Comparator	VCC = 5V			40	mV
VACIO	Input Offset Voltage	Vin = VCC/2			40	mV
	Input Offset Voltage	Vin = VCC/2
IACLK	Analog Comparator	VCC = 5V	-50		50	nA
IACLK	Input Leakage Current	Vin = VCC/2	-50		50	nA
	Input Leakage Current	Vin = VCC/2
tACID	Analog Comparator	VCC = 2.7V		750		ns
tACID	Initialization Delay	VCC = 5.0V		500		ns
	Initialization Delay	VCC = 5.0V		500
tACID	Analog Comparator	VCC = 2.7V		750		ns
tACID	Propagation Delay	VCC = 5.0V		500		ns
	Propagation Delay	VCC = 5.0V		500
Notes: 1.	“Max” means the highest value where the pin is guaranteed to be read as low

2.“Min” means the lowest value where the pin is guaranteed to be read as high

3.Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:

TQFP and MLF Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 300 mA.

3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 150 mA. 4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 150 mA.

5] The sum of all IOL, for ports F0 - F7, should not exceed 200 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.

4.Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:

TQFP and MLF Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports A0 - A7, G2, C3 - C7 should not exceed 300 mA.

3] The sum of all IOH, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 150 mA. 4] The sum of all IOH, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 150 mA.

5] The sum of all IOH, for ports F0 - F7, should not exceed 200 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.

5.Minimum VCC for Power-down is 2.5V.

323

2467K–AVR–04/04

External Clock Drive

Waveforms

External Clock Drive

Figure 152. External Clock Drive Waveforms

VIH1

VIL1

Table 132. External Clock Drive

		VCC = 2.7V to 5.5V			VCC = 4.5V to 5.5V
Symbol	Parameter	Min		Max	Min	Max	Units

1/tCLCL	Oscillator Frequency	0		8	0	16	MHz
tCLCL	Clock Period	125			62.5		ns
tCHCX	High Time	50			25		ns
tCLCX	Low Time	50			25		ns
tCLCH	Rise Time			1.6		0.5	µs
tCHCL	Fall Time			1.6		0.5	µs
	Change in period from
∆tCLCL	one clock cycle to the			2		2	%
∆tCLCL	next
Table 133. External RC Oscillator, Typical Frequencies

	R [kΩ]		C [pF]			f

	100		70			TBD

	31.5		20			TBD

	6.5		20			TBD

Note: R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type.

324 ATmega128

2467K–AVR–04/04

ATmega128

Two-wire Serial Interface Characteristics

Table 134 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega128 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 153.

Table 134. Two-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

VIL

Input Low-voltage

-0.5

0.3 VCC

VIH

Input High-voltage

0.7 VCC

VCC + 0.5

(1)

Hysteresis of Schmitt Trigger Inputs

(2)

–

Vhys

0.05 VCC

(1)

Output Low-voltage

3 mA sink current

0.4

(1)

Rise Time for both SDA and SCL

20 + 0.1C

(3)(2)

300

(1)

Output Fall Time from V

IHmin

to V

ILmax

10 pF < C < 400 pF(3)

20 + 0.1C

(3)(2)

250

tSP(1)

Spikes Suppressed by Input Filter

50(2)

Input Current each I/O Pin

0.1 VCC < Vi < 0.9 VCC

-10

µA

(1)

Capacitance for each I/O Pin

–

SCL

SCL Clock Frequency

(4) > max(16f

, 250kHz)(5)

400

kHz

SCL

fSCL ≤ 100 kHz

VCC – 0,4V

1000ns

Ω

----------------------------

-------------------

Value of Pull-up resistor

3mA

fSCL > 100 kHz

VCC – 0,4V

300ns

Ω

----------------------------

---------------

3mA

tHD;STA

Hold Time (repeated) START Condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tLOW

Low Period of the SCL Clock

fSCL ≤ 100 kHz(6)

4.7

–

µs

fSCL > 100 kHz(7)

1.3

–

µs

tHIGH

High period of the SCL clock

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tSU;STA

Set-up time for a repeated START condition

fSCL ≤ 100 kHz

4.7

–

µs

fSCL > 100 kHz

0.6

–

µs

tHD;DAT

Data hold time

fSCL ≤ 100 kHz

3.45

µs

fSCL > 100 kHz

0.9

µs

tSU;DAT

Data setup time

fSCL ≤ 100 kHz

250

–

fSCL > 100 kHz

100

–

tSU;STO

Setup time for STOP condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tBUF

Bus free time between a STOP and START

fSCL ≤ 100 kHz

4.7

–

µs

condition

Notes: 1. In ATmega128, this parameter is characterized and not 100% tested.

2.Required only for fSCL > 100 kHz.

3.Cb = capacitance of one bus line in pF.

4.fCK = CPU clock frequency

325

2467K–AVR–04/04

SPI Timing

Characteristics

5.This requirement applies to all ATmega128 Two-wire Serial Interface operation. Other

devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement.

6.The actual low period generated by the ATmega128 Two-wire Serial Interface is

(1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7.The actual low period generated by the ATmega128 Two-wire Serial Interface is

(1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega128 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega128 devices, as well as any other device with a proper tLOW acceptance margin.

Figure 153. Two-wire Serial Bus Timing

tof

tHIGH

SCL

tLOW

tSU;STA

tHD;STA

tHD;DAT

SDA

SU;DAT

tSU;STO

tBUF

See Figure 154 and Figure 155 for details.

Table 135. SPI Timing Parameters

			Description			Mode	Min	Typ	Max

1			SCK period			Master		See Table 72

2		SCK high/low				Master		50% duty cycle

3		Rise/Fall time				Master		TBD

4			Setup			Master		10

5			Hold			Master		10

6			Out to SCK			Master		0.5 • tsck
7			SCK to out			Master		10

8		SCK to out high				Master		10

9		SS low to out				Slave		15		ns

10			SCK period			Slave	4 • tck
10			SCK period			Slave	4 • tck
11		SCK high/low(1)				Slave	2 • t
							ck
12		Rise/Fall time				Slave		TBD

13			Setup			Slave	10

14			Hold			Slave	tck
15			SCK to out			Slave		15

16		SCK to			high	Slave	20
16		SCK to		SS	high	Slave	20

17			high to tri-state			Slave		10
17		SS	high to tri-state			Slave		10
18		SS low to SCK				Slave	20

Note:	1. In SPI Programming mode the minimum SCK high/low period is:

-2 tCLCL for fCK < 12 MHz

-3 tCLCL for fCK >12 MHz

326 ATmega128

2467K–AVR–04/04

ATmega128

Figure 154. SPI Interface Timing Requirements (Master Mode)

SS
6			1
SCK
(CPOL = 0)
		2	2
SCK
(CPOL = 1)
4	5		3
MISO	MSB	...	LSB
(Data Input)	MSB	...	LSB
(Data Input)
		7	8
MOSI	MSB	...	LSB
(Data Output)	MSB	...	LSB
(Data Output)

Figure 155. SPI Interface Timing Requirements (Slave Mode)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(Data Input)

MISO

(Data Output)

18
9			10	16
9
		11	11
13	14			12
	MSB	...	LSB
		15		17
	MSB	...	LSB	X

327

2467K–AVR–04/04

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