- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Register Description for I/O Ports
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •Port E Data Register – PORTE
- •Port F Data Register – PORTF
- •Port G Data Register – PORTG
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Section – BLS
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics – Preliminary Data
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. I
- •ATmega128 Rev. H
- •ATmega128 Rev. G
- •ATmega128 Rev. F
- •Datasheet Change Log for ATmega128
- •Changes from Rev. 2467J-12/03 to Rev. 2467K-03/04
- •Changes from Rev. 2467I-09/03 to Rev. 2467J-12/03
- •Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03
- •Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03
- •Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02
- •Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02
- •Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02
- •Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02
- •Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02
- •Table of Contents
Virtual Flash Page Read
Register
Programming Algorithm
Figure 150. Virtual Flash Page Load Register
STROBES
State
machine
TDI
ADDRESS
Flash
EEPROM
Fuses
Lock Bits
D
A
T
A
TDO
The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte by byte. The first eight cycles are used to transfer the first byte to the internal Shift Register, and the bits that are shifted out during these 8 cycles should be ignored. Following this initialization, data are shifted out starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to read one full Flash page to verify programming.
Figure 151. Virtual Flash Page Read Register
STROBES
State
machine
TDI
ADDRESS
Flash
EEPROM
Fuses
Lock Bits
D
A
T
A
TDO
All references below of type “1a”, “1b”, and so on, refer to Table 131.
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ATmega128 |
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Entering Programming Mode |
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1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. |
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2. |
Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Pro- |
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gramming Enable Register. |
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Leaving Programming Mode |
1. Enter JTAG instruction PROG_COMMANDS. |
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2. |
Disable all programming instructions by using no operation instruction 11a. |
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3. |
Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the pro- |
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gramming Enable Register. |
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4. |
Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. |
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Performing Chip Erase |
1. |
Enter JTAG instruction PROG_COMMANDS. |
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2. |
Start chip erase using programming instruction 1a. |
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3. |
Poll for chip erase complete using programming instruction 1b, or wait for |
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tWLRH_CE (refer to Table Note: on page 303). |
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Programming the Flash |
Before programming the Flash a Chip Erase must be performed. See “Performing Chip |
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Erase” on page 319. |
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1. |
Enter JTAG instruction PROG_COMMANDS. |
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2. |
Enable Flash write using programming instruction 2a. |
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3. |
Load address high byte using programming instruction 2b. |
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4. |
Load address low byte using programming instruction 2c. |
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5. |
Load data using programming instructions 2d, 2e and 2f. |
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6. |
Repeat steps 4 and 5 for all instruction words in the page. |
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7. |
Write the page using programming instruction 2g. |
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8. |
Poll for Flash write complete using programming instruction 2h, or wait for tWLRH |
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(refer to Table Note: on page 303). |
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9. |
Repeat steps 3 to 7 until all data have been programmed. |
A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction:
1.Enter JTAG instruction PROG_COMMANDS.
2.Enable Flash write using programming instruction 2a.
3.Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 124 on page 294) is used to address within one page and must be written as 0.
4.Enter JTAG instruction PROG_PAGELOAD.
5.Load the entire page by shifting in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page.
6.Enter JTAG instruction PROG_COMMANDS.
7.Write the page using programming instruction 2g.
8.Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to Table Note: on page 303).
9.Repeat steps 3 to 8 until all data have been programmed.
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Reading the Flash |
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1. |
Enter JTAG instruction PROG_COMMANDS. |
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2. |
Enable Flash read using programming instruction 3a. |
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3. |
Load address using programming instructions 3b and 3c. |
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4. |
Read data using programming instruction 3d. |
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Repeat steps 3 and 4 until all data have been read. |
A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction:
1.Enter JTAG instruction PROG_COMMANDS.
2.Enable Flash read using programming instruction 3a.
3.Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 124 on page 294) is used to address within one page and must be written as 0.
4.Enter JTAG instruction PROG_PAGEREAD.
5.Read the entire page by shifting out all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Remember that the first 8 bits shifted out should be ignored.
6.Enter JTAG instruction PROG_COMMANDS.
7.Repeat steps 3 to 6 until all data have been read.
Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed. See “Performing Chip Erase” on page 319.
1.Enter JTAG instruction PROG_COMMANDS.
2.Enable EEPROM write using programming instruction 4a.
3.Load address high byte using programming instruction 4b.
4.Load address low byte using programming instruction 4c.
5.Load data using programming instructions 4d and 4e.
6.Repeat steps 4 and 5 for all data bytes in the page.
7.Write the data using programming instruction 4f.
8.Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to Table Note: on page 303).
9.Repeat steps 3 to 8 until all data have been programmed.
Note that the PROG_PAGELOAD instruction can not be used when programming the
EEPROM
Reading the EEPROM |
1. |
Enter JTAG instruction PROG_COMMANDS. |
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2. |
Enable EEPROM read using programming instruction 5a. |
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3. |
Load address using programming instructions 5b and 5c. |
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4. |
Read data using programming instruction 5d. |
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5. |
Repeat steps 3 and 4 until all data have been read. |
Note that the PROG_PAGEREAD instruction can not be used when reading the
EEPROM
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ATmega128 |
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Programming the Fuses |
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1. |
Enter JTAG instruction PROG_COMMANDS. |
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2. |
Enable Fuse write using programming instruction 6a. |
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3. |
Load data byte using programming instructions 6b. A bit value of “0” will program |
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the corresponding fuse, a “1” will unprogram the fuse. |
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4. |
Write Extended Fuse byte using programming instruction 6c. |
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5. |
Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH |
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(refer to Table Note: on page 303). |
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6. |
Load data byte using programming instructions 6e. A bit value of “0” will program |
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the corresponding fuse, a “1” will unprogram the fuse. |
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7. |
Write Fuse high byte using programming instruction 6f. |
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8. |
Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH |
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(refer to Table Note: on page 303). |
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9. |
Load data byte using programming instructions 6h. A “0” will program the fuse, a |
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“1” will unprogram the fuse. |
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10. |
Write Fuse low byte using programming instruction 6i. |
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11. |
Poll for Fuse write complete using programming instruction 6j, or wait for tWLRH |
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(refer to Table Note: on page 303). |
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Programming the Lock Bits |
1. |
Enter JTAG instruction PROG_COMMANDS. |
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2. |
Enable Lock bit write using programming instruction 7a. |
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3. |
Load data using programming instructions 7b. A bit value of “0” will program the |
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corresponding lock bit, a “1” will leave the lock bit unchanged. |
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4. |
Write Lock bits using programming instruction 7c. |
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5. |
Poll for Lock bit write complete using programming instruction 7d, or wait for |
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tWLRH (refer to Table Note: on page 303). |
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Reading the Fuses and Lock |
1. |
Enter JTAG instruction PROG_COMMANDS. |
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Bits |
2. |
Enable Fuse/Lock bit read using programming instruction 8a. |
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3. |
To read all Fuses and Lock bits, use programming instruction 8f. |
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To only read Extended Fuse byte, use programming instruction 8b. |
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To only read Fuse high byte, use programming instruction 8c. |
To only read Fuse low byte, use programming instruction 8d.
To only read Lock bits, use programming instruction 8e.
Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS.
2.Enable Signature byte read using programming instruction 9a.
3.Load address $00 using programming instruction 9b.
4.Read first signature byte using programming instruction 9c.
5.Repeat steps 3 and 4 with address $01 and address $02 to read the second and third signature bytes, respectively.
Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS.
2.Enable Calibration byte read using programming instruction 10a.
3.Load address $00 using programming instruction 10b.
4.Read the calibration byte using programming instruction 10c.
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