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Рыбницкий Филиал Приднестровского Государственного Университета им.Т.Г.Шевченко

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AVR / datasheets / atmega_128.pdf

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ATmega128

Figure 138. Programming the EEPROM Waveforms

DATA

0x11

ADDR. HIGH ADDR. LOW

DATA

ADDR. LOW

DATA

XA1

XA0

BS1

XTAL1

RDY/BSY

RESET

+12V

PAGEL

BS2

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the

Flash” on page 296 for details on Command and Address loading):

1.A: Load Command “0000 0010”.

2.G: Load Address High Byte ($00 - $FF).

3.B: Load Address Low Byte ($00 - $FF).

4.Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5.Set BS1 to “1”. The Flash word high byte can now be read at DATA.

6.Set OE to “1”.

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” on page 296 for details on Command and Address loading):

A: Load Command “0000 0011”.

G: Load Address High Byte ($00 - $FF).

B: Load Address Low Byte ($00 - $FF).

Set

to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at

DATA.

Set

to “1”.

Programming the Fuse Low

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming

Bits

the Flash” on page 296 for details on Command and Data loading):

A: Load Command “0100 0000”.

C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

Set BS1 to “0” and BS2 to “0”.

Give

to go high.

a negative pulse and wait for RDY/BSY

299

2467K–AVR–04/04

Programming the Fuse High

	The algorithm for programming the Fuse High bits is as follows (refer to “Programming
Bits	the Flash” on page 296 for details on Command and Data loading):
	1.	A: Load Command “0100 0000”.
	2.	C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
	3.	Set BS1 to “1” and BS2 to “0”. This selects high data byte.
	4.	Give			to go high.
			WR	a negative pulse and wait for RDY/BSY
	5.	Set BS1 to “0”. This selects low data byte.
Programming the Extended	The algorithm for programming the Extended Fuse bits is as follows (refer to “Program-
Fuse Bits	ming the Flash” on page 296 for details on Command and Data loading):
	1.	A: Load Command “0100 0000”.
	2.	C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
	3.	Set BS2 to “1” and BS1 to “0”. This selects extended data byte.
	4.	Give			to go high.
			WR	a negative pulse and wait for RDY/BSY
	5.	Set BS2 to “0”. This selects low data byte.

Figure 139. Programming the Fuses

			Write Fuse Low byte			Write Fuse high byte			Write Extended Fuse byte
	A	C		A	C		A	C
DATA	$40	DATA	XX	$40	DATA	XX	$40	DATA	XX
DATA

XA1

XA0

BS1

BS2

XTAL1

RDY/BSY

RESET +12V

PAGEL

Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 296 for details on Command and Data loading):

1.A: Load Command “0010 0000”.

2.C: Load Data Low Byte. Bit n = “0” programs the Lock bit.

3.Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.


Reading the Fuse and Lock	The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming
Bits	the Flash” on page 296 for details on Command loading):
	1.	A: Load Command “0000 0100”.
	2.	Set				to “0”, BS2 to “0”, and BS1 to “0”. The status of the Fuse Low bits can
				OE
		now be read at DATA (“0” means programmed).
	3.	Set			to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits can
			OE
		now be read at DATA (“0” means programmed).

300 ATmega128

2467K–AVR–04/04

ATmega128

4.Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now be read at DATA (“0” means programmed).

5.Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed).

6.Set OE to “1”.

Figure 140. Mapping Between BS1, BS2 and the Fuseand Lock Bits During Read

Fuse Low Byte	0

			0
			0
Extended Fuse byte	1
	BS2			DATA
				DATA


Lock bits	0

		1
			BS1


Fuse high byte	1

BS2

Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for details on Command and Address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low Byte ($00 - $02).

3.Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.

4.Set OE to “1”.

Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to Programming the Flash for details on Command and Address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low Byte.

3.Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4.Set OE to “1”.

301

2467K–AVR–04/04

Parallel Programming

Figure 141. Parallel Programming Timing, Including some General Timing

Characteristics

Requirements

tXLWL

XTAL1

tXHXL

Data & Contol

tDVXH

tXLDX

(DATA, XA0/1, BS1, BS2)

tBVPH

tPLBX

t BVWL

tWLBX

PAGEL

tPHPL

tWL WH

tPLWL

WLRL

RDY/BSY

tWLRH

Figure 142. Parallel Programming Timing, Loading Sequence with Timing

Requirements

LOAD ADDRESS	LOAD DATA	LOAD DATA LOAD DATA	LOAD ADDRESS
(LOW BYTE)	(LOW BYTE)	(HIGH BYTE)	(LOW BYTE)
	t XLXH	tXLPH	tPLXH
	t XLXH		tPLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note: The timing requirements shown in Figure 141 (i.e. tDVXH, tXHXL, and tXLDX) also apply to loading operation.

302 ATmega128

2467K–AVR–04/04

ATmega128

Figure 143. Parallel Programming Timing, Reading Sequence (Within the Same Page) with Timing Requirements

LOAD ADDRESS		READ DATA		READ DATA	LOAD ADDRESS
(LOW BYTE)		(LOW BYTE)		(HIGH BYTE)	(LOW BYTE)
	tXLOL
XTAL1
			tBHDV

BS1

tOLDV

tOHDZ

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note: The timing requirements shown in Figure 141 (i.e. tDVXH, tXHXL, and tXLDX) also apply to

reading operation.

Table 127.

Parallel Programming Characteristics, VCC = 5 V ± 10%

Symbol

Parameter

Min

Typ

Max

Units

VPP

Programming Enable Voltage

11.5

12.5

IPP

Programming Enable Current

250

µA

tDVXH

Data and Control Valid before XTAL1 High

tXLXH

XTAL1 Low to XTAL1 High

200

tXHXL

XTAL1 Pulse Width High

150

tXLDX

Data and Control Hold after XTAL1 Low

tXLWL

XTAL1 Low to

Low

tXLPH

XTAL1 Low to PAGEL high

tPLXH

PAGEL low to XTAL1 high

150

tBVPH

BS1 Valid before PAGEL High

tPHPL

PAGEL Pulse Width High

150

tPLBX

BS1 Hold after PAGEL Low

tWLBX

BS2/1 Hold after

Low

tPLWL

PAGEL Low to

Low

tBVWL

BS1 Valid to

Low

tWLWH

Pulse Width Low

150

tWLRL

Low

µs

Low to RDY/BSY

tWLRH

High(1)

3.7

4.5

Low to RDY/BSY

tWLRH_CE

High for Chip Erase(2)

7.5

Low to RDY/BSY

tXLOL

XTAL1 Low to

Low

303

2467K–AVR–04/04

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