Performing a Page Write

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Рыбницкий Филиал Приднестровского Государственного Университета им.Т.Г.Шевченко

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		ATmega128

Performing Page Erase by
	To execute page erase, set up the address in the Z-pointer and RAMPZ, write

SPM	“X0000011” to SPMCSR and execute SPM within four clock cycles after writing
	SPMCSR. The data in R1 and R0 is ignored. The page address must be written to
	PCPAGE in the Z-register. Other bits in the Z-pointer must be written zero during this
	operation.
	• Page Erase to the RWW section: The NRWW section can be read during the page
	erase.
	• Page Erase to the NRWW section: The CPU is halted during the operation.
Filling the Temporary Buffer	To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
(Page Loading)	“00000001” to SPMCSR and execute SPM within four clock cycles after writing
	SPMCSR. The content of PCWORD in the Z-register is used to address the data in the
	temporary buffer. The temporary buffer will auto-erase after a page write operation or by
	writing the RWWSRE bit in SPMCSR. It is also erased after a System Reset. Note that it
	is not possible to write more than one time to each address without erasing the tempo-
	rary buffer.
	Note: If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded
	will be lost.
Performing a Page Write	To execute page write, set up the address in the Z-pointer and RAMPZ, write
	“X0000101” to SPMCSR and execute SPM within four clock cycles after writing
	SPMCSR. The data in R1 and R0 is ignored. The page address must be written to
	PCPAGE. Other bits in the Z-pointer must be written zero during this operation.
	• Page Write to the RWW section: The NRWW section can be read during the page
	write.
	• Page Write to the NRWW section: The CPU is halted during the operation.
Using the SPM Interrupt	If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt
	when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used
	instead of polling the SPMCSR Register in software. When using the SPM interrupt, the
	interrupt vectors should be moved to the BLS section to avoid that an interrupt is
	accessing the RWW section when it is blocked for reading. How to move the interrupts
	is described in “Interrupts” on page 57.
Consideration While Updating	Special care must be taken if the user allows the Boot Loader section to be updated by
BLS	leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can
	corrupt the entire Boot Loader, and further software updates might be impossible. If it is
	not necessary to change the Boot Loader software itself, it is recommended to program
	the Boot Lock bit11 to protect the Boot Loader software from any internal software
	changes.
Prevent Reading the RWW	During Self-Programming (either page erase or page write), the RWW section is always
Section During Self-	blocked for reading. The user software itself must prevent that this section is addressed
Programming	during the Self-Programming operation. The RWWSB in the SPMCSR will be set as
	long as the RWW section is busy. During Self-Programming the interrupt vector table
	should be moved to the BLS as described in “Interrupts” on page 57, or the interrupts
	must be disabled. Before addressing the RWW section after the programming is com-
	pleted, the user software must clear the RWWSB by writing the RWWSRE. See “Simple
	Assembly Code Example for a Boot Loader” on page 285 for an example.

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2467K–AVR–04/04

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.

	Bit	7	6	5	4	3	2	1	0
	R0	1	1	BLB12	BLB11	BLB02	BLB01	1	1

	See Table 109 and Table 110 for how the different settings of the Boot Loader Bits
	affect the Flash access.
	If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed
	if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in
	SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it
	is recommended to load the Z-pointer with $0001 (same as used for reading the Lock
	bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1”
	when writing the lock-bits. When programming the Lock Bits the entire Flash can be
	read during the operation.
EEPROM Write Prevents	Note that an EEPROM write operation will block all software programming to Flash.
Writing to SPMCSR	Reading the Fuses and Lock bits from software will also be prevented during the
	EEPROM write operation. It is recommended that the user checks the status bit (EEWE)
	in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
	Register.

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

Bit	7	6	5	4	3	2	1	0
Rd	–	–	BLB12	BLB11	BLB02	BLB01	LB2	LB1

The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to Table 120 on page 291 for a detailed description and mapping of the Fuse Low bits.

Bit	7	6	5	4	3	2	1	0
Rd	FLB7	FLB6	FLB5	FLB4	FLB3	FLB2	FLB1	FLB0

Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below. Refer to Table 119 on page 291 for detailed description and mapping of the Fuse High bits.

Bit	7	6	5	4	3	2	1	0
Rd	FHB7	FHB6	FHB5	FHB4	FHB3	FHB2	FHB1	FHB0

When reading the Extended Fuse bits, load $0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in

284 ATmega128

2467K–AVR–04/04

ATmega128

the SPMCSR, the value of the Extended Fuse bits (EFB) will be loaded in the destination register as shown below. Refer to Table 118 on page 290 for detailed description and mapping of the Fuse High bits.

Bit	7	6	5	4	3	2	1	0
Rd	–	–	–	–	–	–	EFB1	EFB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one.

Preventing Flash Corruption	During periods of low VCC, the Flash program can be corrupted because the supply volt-
	age is too low for the CPU and the Flash to operate properly. These issues are the same
	as for board level systems using the Flash, and the same design solutions should be
	applied.
	A Flash program corruption can be caused by two situations when the voltage is too low.
	First, a regular write sequence to the Flash requires a minimum voltage to operate cor-
	rectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage
	for executing instructions is too low.
	Flash corruption can easily be avoided by following these design recommendations (one
	is sufficient):
	1. If there is no need for a Boot Loader update in the system, program the Boot
	Loader Lock bits to prevent any Boot Loader software updates.
	2. Keep the AVR RESET active (low) during periods of insufficient power supply
	voltage. This can be done by enabling the internal Brown-out Detector (BOD) if
	the operating voltage matches the detection level. If not, an external low VCC
	Reset Protection circuit can be used. If a Reset occurs while a write operation is
	in progress, the write operation will be completed provided that the power supply
	voltage is sufficient.
	3. Keep the AVR core in Power-down Sleep mode during periods of low VCC. This
	will prevent the CPU from attempting to decode and execute instructions, effec-
	tively protecting the SPMCSR Register and thus the Flash from unintentional
	writes.
Programming Time for Flash	The calibrated RC Oscillator is used to time Flash accesses. Table 112 shows the typi-
when Using SPM	cal programming time for Flash accesses from the CPU.
	Table 112. SPM Programming Time.

Simple Assembly Code Example for a Boot Loader

Symbol	Min Programming Time	Max Programming Time

Flash write (page erase, page write,	3.7 ms	4.5 ms
and write lock bits by SPM)	3.7 ms	4.5 ms
and write lock bits by SPM)

;-the routine writes one page of data from RAM to Flash

;the first data location in RAM is pointed to by the Y pointer

;the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included

;-the routine must be placed inside the boot space

;(at least the Do_spm sub routine). Only code inside NRWW section

can

;be read during self-programming (page erase and page write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

;loophi (r25), spmcsrval (r20)

;storing and restoring of registers is not included in the routine

;register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the

285

2467K–AVR–04/04

Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2		;PAGESIZEB is page size in BYTES, not
words
.org SMALLBOOTSTART
Write_page:
; page erase
ldi	spmcsrval, (1<<PGERS) \| (1<<SPMEN)
call	Do_spm
; re-enable the RWW section
ldi	spmcsrval, (1<<RWWSRE) \| (1<<SPMEN)
call	Do_spm
; transfer data from RAM to Flash page buffer
ldi	looplo, low(PAGESIZEB);init loop variable
ldi	loophi, high(PAGESIZEB);not required for PAGESIZEB<=256
Wrloop:
ld	r0, Y+
ld	r1, Y+
ldi	spmcsrval, (1<<SPMEN)
call	Do_spm
adiw	ZH:ZL, 2
sbiw	loophi:looplo, 2	;use subi for PAGESIZEB<=256
brne	Wrloop
; execute page write
subi	ZL, low(PAGESIZEB)	;restore pointer
sbci	ZH, high(PAGESIZEB)	;not required for PAGESIZEB<=256
ldi	spmcsrval, (1<<PGWRT) \| (1<<SPMEN)
call	Do_spm
; re-enable the RWW section
ldi	spmcsrval, (1<<RWWSRE) \| (1<<SPMEN)
call	Do_spm
; read back and check, optional
ldi	looplo, low(PAGESIZEB);init loop variable
ldi	loophi, high(PAGESIZEB);not required for PAGESIZEB<=256
subi	YL, low(PAGESIZEB)	;restore pointer
sbci	YH, high(PAGESIZEB)
Rdloop:
lpm	r0, Z+
ld	r1, Y+
cpse	r0, r1
jmp	Error
sbiw	loophi:looplo, 1	;use subi for PAGESIZEB<=256
brne	Rdloop

;return to RWW section

;verify that RWW section is safe to read Return:

lds temp1, SPMCSR

sbrs	temp1, RWWSB	; If RWWSB is set, the RWW section is not
ready yet
ret
; re-enable the RWW section
ldi	spmcsrval, (1<<RWWSRE) \| (1<<SPMEN)
call	Do_spm

286 ATmega128

2467K–AVR–04/04

ATmega128

rjmp Return

Do_spm:

;check for previous SPM complete Wait_spm:

lds temp1, SPMCSR sbrc temp1, SPMEN rjmp Wait_spm

;input: spmcsrval determines SPM action

;disable interrupts if enabled, store status in temp2, SREG

cli

;check that no EEPROM write access is present Wait_ee:

sbic EECR, EEWE rjmp Wait_ee

;SPM timed sequence

sts SPMCSR, spmcsrval spm

; restore SREG (to enable interrupts if originally enabled) out SREG, temp2

ret

ATmega128 Boot Loader

In Table 113 through Table 115, the parameters used in the description of the self pro-

Parameters

gramming are given.

Table 113. Boot Size Configuration

Boot

Reset

Boot

Address

Application

Loader

End

(start Boot

Boot

Flash

Application

Loader

BOOTSZ1

BOOTSZ0

Size

Pages

Section

section

Section)

512

$0000 -

$FE00 -

$FDFF

$FE00

words

$FDFF

$FFFF

1024

$0000 -

$FC00 -

$FBFF

$FC00

words

$FBFF

$FFFF

2048

$0000 -

$F800 -

$F7FF

$F800

words

$F7FF

$FFFF

4096

$0000 -

$F000 -

$EFFF

$F000

words

$EFFF

$FFFF

Note:

The different BOOTSZ fuse configurations are shown in Figure 133

Table 114. Read-While-Write Limit(1)

Section

Pages

Address

Read-While-Write section (RWW)

480

$0000 - $EFFF

No Read-While-Write section (NRWW)

$F000 - $FFFF

Note:

For details about these two section, see “No Read-While-Write Section – NRWW” on

page 277 and “Read-While-Write Section – RWW” on page 277

287

2467K–AVR–04/04

Table 115. Explanation of Different Variables Used in Figure 134 and the Mapping to the Z-Pointer(3)

		Corresponding	Description(2)
Variable		Z-value	Description(2)
PCMSB	15		Most significant bit in the program counter. (The
PCMSB			program counter is 16 bits PC[15:0])
			program counter is 16 bits PC[15:0])

	6		Most significant bit which is used to address the
PAGEMSB			words within one page (128 words in a page
			requires 7 bits PC [6:0]).

		Z16(1)	Bit in Z-register that is mapped to PCMSB.
ZPCMSB			Because Z0 is not used, the ZPCMSB equals
			PCMSB + 1.

		Z7	Bit in Z-register that is mapped to PAGEMSB.
ZPAGEMSB			Because Z0 is not used, the ZPAGEMSB
			equals PAGEMSB + 1.

PCPAGE	PC[15:7]	Z16(1):Z7	Program counter page address: Page select, for
PCPAGE			page erase and page write
			page erase and page write

	PC[6:0]	Z7:Z1	Program counter word address: Word select, for
PCWORD			filling temporary buffer (must be zero during
			page write operation)

Notes: 1. The Z-register is only 16 bits wide. Bit 16 is located in the RAMPZ register in the I/O map.

2.Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.

3.See “Addressing the Flash During Self-Programming” on page 281 for details about the use of Z-pointer during self-programming.

288 ATmega128

2467K–AVR–04/04

Memory

Programming

Program and Data

Memory Lock Bits

2467K–AVR–04/04

ATmega128

The ATmega128 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 117. The Lock bits can only be erased to “1” with the Chip Erase command.

Table 116. Lock Bit Byte

Lock Bit Byte	Bit No.	Description	Default Value

	7	–	1 (unprogrammed)

	6	–	1 (unprogrammed)

BLB12	5	Boot lock bit	1 (unprogrammed)

BLB11	4	Boot lock bit	1 (unprogrammed)

BLB02	3	Boot lock bit	1 (unprogrammed)

BLB01	2	Boot lock bit	1 (unprogrammed)

LB2	1	Lock bit	1 (unprogrammed)

LB1	0	Lock bit	1 (unprogrammed)

Note: “1” means unprogrammed, “0´means programmed

Table 117. Lock Bit Protection Modes

Memory Lock Bits			Protection Type

LB mode	LB2	LB1

1	1	1	No memory lock features enabled.

			Further programming of the Flash and EEPROM is
2	1	0	disabled in Parallel and SPI/JTAG Serial Programming
2	1	0	mode. The Fuse bits are locked in both Serial and Parallel
			mode. The Fuse bits are locked in both Serial and Parallel
			Programming mode.(1)
			Further programming and verification of the Flash and
3	0	0	EEPROM is disabled in Parallel and SPI/JTAG Serial
3	0	0	Programming mode. The Fuse bits are locked in both
			Programming mode. The Fuse bits are locked in both
			Serial and Parallel Programming mode.(1)
BLB0 mode	BLB02	BLB01

1	1	1	No restrictions for SPM or (E)LPM accessing the
1	1	1	Application section.
			Application section.

2	1	0	SPM is not allowed to write to the Application section.

			SPM is not allowed to write to the Application section, and
			(E)LPM executing from the Boot Loader section is not
3	0	0	allowed to read from the Application section. If interrupt
			vectors are placed in the Boot Loader section, interrupts
			are disabled while executing from the Application section.

			(E)LPM executing from the Boot Loader section is not
4	0	1	allowed to read from the Application section. If interrupt
4	0	1	vectors are placed in the Boot Loader section, interrupts
			vectors are placed in the Boot Loader section, interrupts
			are disabled while executing from the Application section.

BLB1 mode	BLB12	BLB11

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Performing a Page Write

Using the SPM Interrupt

Setting the Boot Loader Lock Bits by SPM

Reading the Fuse and Lock Bits from Software

Preventing Flash Corruption

Simple Assembly Code Example for a Boot Loader