- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Register Description for I/O Ports
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •Port E Data Register – PORTE
- •Port F Data Register – PORTF
- •Port G Data Register – PORTG
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Section – BLS
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics – Preliminary Data
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. I
- •ATmega128 Rev. H
- •ATmega128 Rev. G
- •ATmega128 Rev. F
- •Datasheet Change Log for ATmega128
- •Changes from Rev. 2467J-12/03 to Rev. 2467K-03/04
- •Changes from Rev. 2467I-09/03 to Rev. 2467J-12/03
- •Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03
- •Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03
- •Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02
- •Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02
- •Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02
- •Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02
- •Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02
- •Table of Contents
ATmega128
ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH).
For single ended conversion, the result is
ADC VIN 1024
= --------------------------
VREF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 97 on page 245 and Table 98 on page 245). 0x000 represents analog
ground, and 0x3FF represents the selected reference voltage minus one LSB.
If differential channels are used, the result is
ADC (VPOS – VNEG) GAIN 512
= -----------------------------------------------------------------------
VREF
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, GAIN the selected gain factor, and VREF the selected voltage reference. The result is presented in two’s complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user wants to perform a quick polarity check of the results, it is sufficient to read the MSB of the result (ADC9 in ADCH). If this bit is one, the result is negative, and if this bit is zero, the result is positive. Figure 119 shows the decoding of the differential input range.
Table 96 shows the resulting output codes if the differential input channel pair (ADCn -
ADCm) is selected with a gain of GAIN and a reference voltage of VREF.
243
2467K–AVR–04/04
Figure 119. Differential Measurement Range
|
Output Code |
|
|
0x1FF |
|
|
0x000 |
|
- VREF/GAIN |
0x3FF |
0 |
|
|
0x200 |
VREF/GAIN Differential Input
Voltage (Volts)
Table 96. Correlation Between Input Voltage and Output Codes
VADCn |
Read code |
Corresponding decimal value |
VADCm + VREF /GAIN |
0x1FF |
511 |
|
|
|
VADCm + 0.999 VREF /GAIN |
0x1FF |
511 |
VADCm + 0.998 VREF /GAIN |
0x1FE |
510 |
... |
... |
... |
|
|
|
VADCm + 0.001 VREF /GAIN |
0x001 |
1 |
VADCm |
0x000 |
0 |
VADCm - 0.001 VREF /GAIN |
0x3FF |
-1 |
|
|
|
... |
... |
... |
|
|
|
VADCm - 0.999 VREF /GAIN |
0x201 |
-511 |
VADCm - VREF /GAIN |
0x200 |
-512 |
|
|
|
Example:
ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)
Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270
244 ATmega128
2467K–AVR–04/04
ADC Multiplexer Selection
Register – ADMUX
2467K–AVR–04/04
ATmega128
ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
REFS1 |
REFS0 |
ADLAR |
MUX4 |
MUX3 |
MUX2 |
MUX1 |
MUX0 |
ADMUX |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
• Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 97. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
Table 97. Voltage Reference Selections for ADC
REFS1 |
REFS0 |
Voltage Reference Selection |
|
|
|
0 |
0 |
AREF, Internal Vref turned off |
|
|
|
0 |
1 |
AVCC with external capacitor at AREF pin |
|
|
|
1 |
0 |
Reserved |
|
|
|
1 |
1 |
Internal 2.56V Voltage Reference with external capacitor at AREF pin |
|
|
|
•Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register – ADCL and ADCH” on page 247.
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 98 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
Table 98. Input Channel and Gain Selections
|
Single Ended |
Positive Differential |
Negative Differential |
|
MUX4..0 |
Input |
Input |
Input |
Gain |
|
|
|
|
|
00000 |
ADC0 |
|
|
|
|
|
|
|
|
00001 |
ADC1 |
|
|
|
|
|
|
|
|
00010 |
ADC2 |
|
|
|
|
|
|
|
|
00011 |
ADC3 |
N/A |
|
|
|
|
|
|
|
00100 |
ADC4 |
|
|
|
|
|
|
|
|
00101 |
ADC5 |
|
|
|
|
|
|
|
|
00110 |
ADC6 |
|
|
|
|
|
|
|
|
00111 |
ADC7 |
|
|
|
01000 |
|
ADC0 |
ADC0 |
10x |
|
|
|
|
|
01001 |
|
ADC1 |
ADC0 |
10x |
|
|
|
|
|
245
Table 98. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Input Channel and Gain Selections (Continued) |
|
|||||||
|
|
|
|
|
|
|||
|
Single Ended |
|
Positive Differential |
Negative Differential |
|
|||
MUX4..0 |
Input |
|
Input |
Input |
Gain |
|||
|
|
|
|
|
|
|||
01010 |
|
|
ADC0 |
ADC0 |
200x |
|||
|
|
|
|
|
|
|||
01011 |
|
|
ADC1 |
ADC0 |
200x |
|||
|
|
|
|
|
|
|||
01100 |
|
|
ADC2 |
ADC2 |
10x |
|||
|
|
|
|
|
|
|||
01101 |
|
|
ADC3 |
ADC2 |
10x |
|||
|
|
|
|
|
|
|||
01110 |
|
|
ADC2 |
ADC2 |
200x |
|||
|
|
|
|
|
|
|||
01111 |
|
|
ADC3 |
ADC2 |
200x |
|||
|
|
|
|
|
|
|||
10000 |
|
|
ADC0 |
ADC1 |
1x |
|||
|
|
|
|
|
|
|||
10001 |
|
|
ADC1 |
ADC1 |
1x |
|||
|
|
|
|
|
|
|||
10010 |
N/A |
|
ADC2 |
ADC1 |
1x |
|||
|
|
|
|
|
|
|||
10011 |
|
|
ADC3 |
ADC1 |
1x |
|||
|
|
|
|
|
|
|||
10100 |
|
|
ADC4 |
ADC1 |
1x |
|||
|
|
|
|
|
|
|||
10101 |
|
|
ADC5 |
ADC1 |
1x |
|||
|
|
|
|
|
|
|||
10110 |
|
|
ADC6 |
ADC1 |
1x |
|||
|
|
|
|
|
|
|||
10111 |
|
|
ADC7 |
ADC1 |
1x |
|||
|
|
|
|
|
|
|||
11000 |
|
|
ADC0 |
ADC2 |
1x |
|||
|
|
|
|
|
|
|||
11001 |
|
|
ADC1 |
ADC2 |
1x |
|||
|
|
|
|
|
|
|||
11010 |
|
|
ADC2 |
ADC2 |
1x |
|||
|
|
|
|
|
|
|||
11011 |
|
|
ADC3 |
ADC2 |
1x |
|||
|
|
|
|
|
|
|||
11100 |
|
|
ADC4 |
ADC2 |
1x |
|||
11101 |
|
|
ADC5 |
ADC2 |
1x |
|||
11110 |
1.23V (VBG) |
|
N/A |
|
|
|||
11111 |
0V (GND) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ADC Control and Status
Register A – ADCSRA
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ADEN |
ADSC |
ADFR |
ADIF |
ADIE |
ADPS2 |
ADPS1 |
ADPS0 |
ADCSRA |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC.
246 ATmega128
2467K–AVR–04/04