- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Register Description for I/O Ports
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •Port E Data Register – PORTE
- •Port F Data Register – PORTF
- •Port G Data Register – PORTG
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Section – BLS
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics – Preliminary Data
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. I
- •ATmega128 Rev. H
- •ATmega128 Rev. G
- •ATmega128 Rev. F
- •Datasheet Change Log for ATmega128
- •Changes from Rev. 2467J-12/03 to Rev. 2467K-03/04
- •Changes from Rev. 2467I-09/03 to Rev. 2467J-12/03
- •Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03
- •Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03
- •Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02
- •Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02
- •Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02
- •Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02
- •Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02
- •Table of Contents
Input Capture Unit
TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 121.
The Timer/Counter Overflow (TOVn) flag is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.
The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 48. The elements of the block diagram that are not directly a part of the input capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number.
Figure 48. Input Capture Unit Block Diagram
DATA BUS (8-bit)
TEMP (8-bit)
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ICRnH (8-bit) |
ICRnL (8-bit) |
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TCNTnH (8-bit) |
TCNTnL (8-bit) |
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WRITE |
ICRn (16-bit Register) |
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TCNTn (16-bit Counter) |
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ACO* |
ACIC* |
ICNC |
ICES |
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Analog |
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Comparator |
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Noise |
Edge |
ICFn (Int.Req.) |
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Canceler |
Detector |
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ICPn |
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Note: The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not
Timer/Counter3.
When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn), alternatively on the analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn Register. If enabled (TICIEn = 1), the input capture flag generates an input capture interrupt. The ICFn flag is automatically cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O bit location.
116 ATmega128
2467K–AVR–04/04
ATmega128
Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte Temporary Register (TEMP). When the CPU reads the
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ICRnH I/O location it will access the TEMP Register. |
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The ICRn Register can only be written when using a Waveform Generation mode that |
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utilizes the ICRn Register for defining the counter’s TOP value. In these cases the |
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Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be |
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written to the ICRn Register. When writing the ICRn Register the high byte must be writ- |
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ten to the ICRnH I/O location before the low byte is written to ICRnL. |
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For more information on how to access the 16-bit registers refer to “Accessing 16-bit |
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Registers” on page 112. |
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Input Capture Trigger Source |
The main trigger source for the input capture unit is the Input Capture Pin (ICPn). |
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Timer/Counter1 can alternatively use the analog comparator output as trigger source for |
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the input capture unit. The Analog Comparator is selected as trigger source by setting |
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the analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and |
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Status Register (ACSR). Be aware that changing trigger source can trigger a capture. |
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The input capture flag must therefore be cleared after the change. |
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Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are |
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sampled using the same technique as for the Tn pin (Figure 59 on page 143). The edge |
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detector is also identical. However, when the noise canceler is enabled, additional logic |
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is inserted before the edge detector, which increases the delay by four system clock |
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cycles. Note that the input of the noise canceler and edge detector is always enabled |
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unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to |
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define TOP. |
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An input capture can be triggered by software by controlling the port of the ICPn pin. |
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Noise Canceler |
The noise canceler improves noise immunity by using a simple digital filtering scheme. |
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The noise canceler input is monitored over four samples, and all four must be equal for |
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changing the output that in turn is used by the edge detector. |
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The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit |
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in Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler intro- |
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duces additional four system clock cycles of delay from a change applied to the input, to |
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the update of the ICRn Register. The noise canceler uses the system clock and is there- |
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fore not affected by the prescaler. |
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Using the Input Capture Unit |
The main challenge when using the input capture unit is to assign enough processor |
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capacity for handling the incoming events. The time between two events is critical. If the |
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processor has not read the captured value in the ICRn Register before the next event |
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occurs, the ICRn will be overwritten with a new value. In this case the result of the cap- |
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ture will be incorrect. |
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When using the input capture interrupt, the ICRn Register should be read as early in the |
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interrupt handler routine as possible. Even though the input capture interrupt has rela- |
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tively high priority, the maximum interrupt response time is dependent on the maximum |
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number of clock cycles it takes to handle any of the other interrupt requests. |
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Using the input capture unit in any mode of operation when the TOP value (resolution) is |
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actively changed during operation, is not recommended. |
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Measurement of an external signal’s duty cycle requires that the trigger edge is changed |
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after each capture. Changing the edge sensing must be done as early as possible after |
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the ICRn Register has been read. After a change of the edge, the input capture flag |
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2467K–AVR–04/04 |
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