ATmega128
Timer/Counter Prescaler Figure 45. Prescaler for Timer/Counter0
clkI/O |
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clkT0S |
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10-BIT T/C PRESCALER |
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TOSC1 |
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Clear |
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/8 |
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/32 |
/64 |
/128 |
/256 |
/1024 |
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T0S |
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T0S |
T0S |
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T0S |
T0S |
T0S |
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AS0 |
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clk |
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clk |
clk |
clk |
clk |
clk |
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PSR0 |
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0 |
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CS00 |
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CS01 |
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CS02 |
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Special Function IO Register –
SFIOR
TIMER/COUNTER0 CLOCK SOURCE clkT0
The clock source for Timer/Counter0 is named clkT0. clkT0 is by default connected to the main system clock clkI/O. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter0 as a Real Time Counter (RTC). When AS0 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter0. The Oscillator is optimized for use with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not recommended.
For Timer/Counter0, the possible prescaled selections are: clkT0S/8, clkT0S/32, clkT0S/64,
clkT0S/128, clkT0S/256, and clkT0S/1024. Additionally, clkT0S as well as 0 (stop) may be selected. Setting the PSR0 bit in SFIOR resets the prescaler. This allows the user to
operate with a predictable prescaler.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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TSM |
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– |
– |
ACME |
PUD |
PSR0 |
PSR321 |
SFIOR |
Read/Write |
R/W |
R |
R |
R |
R/W |
R/W |
R/W |
R/W |
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Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR0 and PSR321 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start counting simultaneously.
• Bit 1 – PSR0: Prescaler Reset Timer/Counter0
107
2467K–AVR–04/04
When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If this bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set.
108 ATmega128
2467K–AVR–04/04