ATmega128
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
Assembly Code Example
WDT_off:
; Write logical one to WDCE and WDE ldi r16, (1<<WDCE)|(1<<WDE)
out WDTCR, r16
; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret
C Code Example
void WDT_off(void)
{
/* Write logical one to WDCE and WDE */ WDTCR = (1<<WDCE) | (1<<WDE);
/* Turn off WDT */ WDTCR = 0x00;
}
Timed Sequences for Changing the Configuration of the Watchdog Timer
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The sequence for changing configuration differs slightly between the three safety levels. |
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Separate procedures are described for each level. |
Safety Level 0 |
This mode is compatible with the Watchdog operation found in ATmega103. The Watch- |
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dog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without |
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any restriction. The time-out period can be changed at any time without restriction. To |
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disable an enabled Watchdog Timer, the procedure described on page 53 (WDE bit |
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description) must be followed. |
Safety Level 1 |
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the |
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WDE bit to 1 without any restriction. A timed sequence is needed when changing the |
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Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an |
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enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following proce- |
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dure must be followed: |
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1. In the same operation, write a logic one to WDCE and WDE. A logic one must be |
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written to WDE regardless of the previous value of the WDE bit. |
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2. Within the next four clock cycles, in the same operation, write the WDE and WDP |
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bits as desired, but with the WDCE bit cleared. |
Safety Level 2 |
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read |
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as one. A timed sequence is needed when changing the Watchdog Time-out period. To |
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change the Watchdog Time-out, the following procedure must be followed: |
55
2467K–AVR–04/04
1.In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence.
2.Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
56 ATmega128
2467K–AVR–04/04