--Description:
--Dependencies:
--Revision:
--Revision 0.01 - File Created
--Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Uncomment the following library declaration if using
--arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
--Uncomment the following library declaration if instantiating
--any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity button is
Port ( btn : in STD_LOGIC; i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
o1 : out STD_LOGIC;
o2 : out STD_LOGIC); end button;
architecture Behavioral of button is
begin
process(btn, i1, i2) begin
if btn = '1' then o1 <= not i1; o2 <= not i2;
else
o1 <= i1;
o2 <= i2; end if;
end process;
end Behavioral;
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