литература / verilog_lec
.pdfEE577b ¾ Verilog for Behavioral Modeling
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Outline |
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Introduction |
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Data types |
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Expressions |
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Assignments |
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Behavioral modeling |
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Hierarchical structures |
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System (built-in) functions |
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Example |
Nestoras Tzartzanis |
71 |
February 3, 1998 |
EE577b ¾ Verilog for Behavioral Modeling
Simulating a Simple Instruction Set Architecture
·A baby-instruction set:
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MV: Rd ¬ sign_ext(Imm) |
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ADD: Rd ¬ Rd + Rsr |
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XOR: Rd ¬ Rd Å Rsr |
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·No memory instructions
·No control transfer instructions
·If the operand of an instruction is written by the previous one, the old value is read
Nestoras Tzartzanis |
72 |
February 3, 1998 |
EE577b ¾ Verilog for Behavioral Modeling
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Block Diagram ¾ Data Path |
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I-Memory |
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CPU |
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Counter |
ALU |
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PC |
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Register |
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File |
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Reset |
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Instruction |
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Decoder |
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Nestoras Tzartzanis |
73 |
February 3, 1998 |
EE577b ¾ Verilog for Behavioral Modeling
A Data-Memory Example
Test Module |
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Accessing the |
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Memory |
D-Memory |
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Data |
Rd/Wr |
∙An example where a module port should be declared as inout (i.e., the data bus)
∙Assuming a single phase clocking scheme, the data bus is actively driven by the test module during the first half cycle and by the memory during the second half cycle
∙Temporary register data type variables are required from both sides
∙The assign-statement should be used
Nestoras Tzartzanis |
74 |
February 3, 1998 |