литература / Verilog module introduction and Combinational
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Index and Slice
•VHDL
–Use to and downto to specify slice
–Concatenation &
•c_bus(3 downto 0) <= b_bus(7 downto 4);
•c_bus(5 downto 0) <= b_bus(7) & a_bus(6 downto 3) & ‘0’;
•Verilog
–Use colon :
–Concatenation {,}
•assign c_bus[3:0] = b_bus[7:4];
•assign c_bus[5:0] = {b_bus[7], a_bus[6:3], 1’b0};
Jim Duckworth, WPI |
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Verilog Module Rev A |
Internal wires
• Declare internal wires:
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Verilog Module Rev A |
Sequential Statements
•VHDL
–reside in process statement
•Verilog
–reside in an always statement
–if statements (no endif)
–case statements (endcase)
–for, repeat while loop statements
–Note: use begin and end to block sequential statements
Jim Duckworth, WPI |
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Verilog Module Rev A |
Decoder – always statement
•2 to 4 decoder with enable
•Combinational logic using always statement with sensitivity list
–similar to VHDL process – for cyclic behavior
–(@) event control operator
–begin .. end block statement
–note reg for y
Jim Duckworth, WPI |
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Verilog Module Rev A |
Decoder (cont’d)
•Combinational logic using always statement with sensitivity list
–similar to VHDL process – for cyclic behavior
–(@) event control operator
–begin .. end block statement
•Statements execute sequentially
–if statement
–case statement
•Note: case expression can concatenate signals ({,})
–Sensitivity list
•(a or b or c)
•Verilog 2001 allows comma-separated list (a, b, c)
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Verilog Module Rev A |
Decoder – CASE statement
•CASE is better for this type of design - no priority
–Exactly same logic produced
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Verilog Module Rev A |
Decoder – 3 to 8 with CASE
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MUX example
•Example multiplexer with conditional operator
•Selects different values for the target signal
–priority associated with series of conditions
–(similar to an IF statement)
i0 
i1 
i2 
q
i3 
a b
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Verilog Module Rev A |
Synthesis Results – Technology Schematic
O = ((I0 * I1 * I3) + (!I0 * I1 * I4) + (!I0 * !I1 * I5) + (I0 * !I1 * I2));
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Mux – with CASE statement
• Include all inputs on sensitivity list
Elaborating module <mux_case>.
WARNING:HDLCompiler:91 - "C:\ece3829\mux_case\mux_case.v" Line 34: Signal <i> missing in the sensitivity list is added for synthesis purposes. HDL and postsynthesis simulations may differ as a result.
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