- •1 Seeing: Blazing Processing Characteristics
- •1.1 An Infinite Reservoir of Information
- •1.2 Speed
- •1.3 Illusions
- •1.4 Recognition Evolvement
- •1.5 Basic-Level Categorization
- •1.6 Memory Capacity and Access
- •1.7 Summary
- •2.1 Structural Variability Independence
- •2.2 Viewpoint Independence
- •2.3 Representation and Evolvement
- •2.3.1 Identification Systems
- •2.3.3 Template Matching
- •2.3.4 Scene Recognition
- •2.4 Recapitulation
- •2.5 Refining the Primary Engineering Goal
- •3 Neuroscientific Inspiration
- •3.1 Hierarchy and Models
- •3.2 Criticism and Variants
- •3.3 Speed
- •3.5 Alternative Shape Recognition
- •3.6 Insight from Cases of Visual Agnosia
- •3.7 Neuronal Level
- •3.8 Recapitulation and Conclusion
- •4 Neuromorphic Tools
- •4.1 The Transistor
- •4.2 A Synaptic Circuit
- •4.3 Dendritic Compartments
- •4.4 An Integrate-and-Fire Neuron
- •4.5 A Silicon Cortex
- •4.6 Fabrication Vagrancies require Simplest Models
- •4.7 Recapitulation
- •5 Insight From Line Drawings Studies
- •5.1 A Representation with Polygons
- •5.2 A Representation with Polygons and their Context
- •5.3 Recapitulation
- •6 Retina Circuits Signaling and Propagating Contours
- •6.1 The Input: a Luminance Landscape
- •6.2 Spatial Analysis in the Real Retina
- •6.2.1 Method of Adjustable Thresholds
- •6.2.2 Method of Latencies
- •6.3 The Propagation Map
- •6.4 Signaling Contours in Gray-Scale Images
- •6.4.1 Method of Adjustable Thresholds
- •6.4.2 Method of Latencies
- •6.4.3 Discussion
- •6.5 Recapitulation
- •7 The Symmetric-Axis Transform
- •7.1 The Transform
- •7.2 Architecture
- •7.3 Performance
- •7.4 SAT Variants
- •7.5 Fast Waves
- •7.6 Recapitulation
- •8 Motion Detection
- •8.1 Models
- •8.1.1 Computational
- •8.1.2 Biophysical
- •8.2 Speed Detecting Architectures
- •8.3 Simulation
- •8.4 Biophysical Plausibility
- •8.5 Recapitulation
- •9 Neuromorphic Architectures: Pieces and Proposals
- •9.1 Integration Perspectives
- •9.2 Position and Size Invariance
- •9.3 Architecture for a Template Approach
- •9.4 Basic-Level Representations
- •9.5 Recapitulation
- •10 Shape Recognition with Contour Propagation Fields
- •10.1 The Idea of the Contour Propagation Field
- •10.2 Architecture
- •10.3 Testing
- •10.4 Discussion
- •10.5 Learning
- •10.6 Recapitulation
- •11 Scene Recognition
- •11.1 Objects in Scenes, Scene Regularity
- •11.2 Representation, Evolvement, Gist
- •11.3 Scene Exploration
- •11.4 Engineering
- •11.5 Recapitulation
- •12 Summary
- •12.1 The Quest for Efficient Representation and Evolvement
- •12.2 Contour Extraction and Grouping
- •12.3 Neuroscientific Inspiration
- •12.4 Neuromorphic Implementation
- •12.5 Future Approach
- •Terminology
- •References
- •Index
- •Keywords
- •Abbreviations
42 |
Neuromorphic Tools |
of digital circuits, because they are synchronized by a common clock determining their pace. In contrast, the operation of the analog multichip system needs an asynchronous communication scheme allowing for an exchange of pulses at any time, meaning without relying on any pace maker. Such an asynchronous communication scheme has been invented by several groups (Deiss et al., 1999). I mention here only the one I grew up with, the Silicon Cortex. Originally designed by Mahowald and collaborators, it is now in the process of being refined and tested by Douglas and coworkers (Liu et al., 2001). It uses a socalled Address-Event Representation and basically consists of a list of the specific neuronal connections between chips, whose wiring has to be programmed.
4.6 Fabrication Vagrancies require Simplest Models
There is a little catch though with the emulation of analog circuits. Because the fabrication process of chips does not generate each transistor exactly equally - irrespective whether it contains digital or analog circuits -, there exist slight variations amongst transistors: even if one applies the exact same gate voltage to different transistors on the same chip, the resulting currents flowing through the channels are slightly different which can cause inequalities in summation. These variations do not pose a problem for digital circuits, because they operate in those two extreme states only. Due to this fabrication noise, models that are intended for aVLSI construction, need to be simple and robust. There are a number of simple tricks to counteract to these fabrication variations, for example to increase the transistor size for crucial transistors, like the weight transistor in a synaptic circuit, or to incorporate adaptive circuits into the design like in the silicon retina. Still, simplicity and robustness must accompany any approach to neural modeling in analog circuits.
4.7 Recapitulation
Almost anything goes in analog VLSI circuits - as long as it is simple and robust. One can emulate a palette of synaptic responses, the propagation qualities of dendritic cables and a variety of somatic spiking patterns. A multi-chip architecture enables the communication between several chips and so allows for the distributed emulation of large networks. The really exciting part of this entire approach is, that it can run at reasonable low power, compared to a pure digital approach. Moreover, it is blazingly fast: it runs in real-time like the real visual system does.
Neuromorphic engineering goes of course way beyond of what we have touched in the few paragraphs: there exist silicon cochleas, olfaction systems, visual attention systems and much more (e.g. (Mead,
4.7 Recapitulation |
43 |
1989; Indiveri, 2001)): The few above mentioned circuits suffice to envision an implementation of the networks we will be talking about in some of the remaining chapters (6-10).
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