Ординатура / Офтальмология / Английские материалы / Handbook of Optical Coherence Tomography_Bouma, Tearney_2002

Second, because the use of a polarization interferometer is imposed by the modulation method, artifacts may occur when imaging structures having a very strong polarization backscattering dependence, such as collagen or nerve fibers.

Finally, in contrast with scanning OCM systems, full-field illumination precludes the use of a confocal spatial filter to enhance scattered light rejection. Nevertheless, we show in Section 11.4.2 that when using high NA objectives a resolution similar to that of confocal microscopes is achieved.

11.3.4Signal Acquisition and Processing Instrumentation Principles

When the round-trip optical path difference between the object and reference beams is smaller than the coherence length of the source (see Section 11.4.1), the two beams interfere. The intensity IðtÞ as a function of time on each pixel of the CCD camera can then be expressed as

where I0 is the intensity of the incoherent light (which does not interfere with the light from the reference beam), AS expði SÞ and AR expði RÞ are the complex amplitudes of the mutually coherent waves reflected by the object and by the reference mirror, respectively, and ¼ R S. As described earlier, a photoelastic modulator introduces a sinusoidal phase variation of amplitude and frequency f ¼ !=2 ¼ 50 kHz between the object and reference waves. IðtÞ contains a constant noninterference term and a time-modulated interference term that is proportional to the amplitude AS. Using the nth Bessel function of the first kind Jn, the intensity IðtÞ can be expressed as

The light emitted by the LED is actually also modulated at the resonant modulator’s frequency f ¼ 50 kHz. Four successive square modulations MpðtÞ are applied to the LED supply current (Fig. 6). The square modulations MpðtÞ can be

The intensity received by each pixel of the CCD camera is then the product IðtÞ MpðtÞ. Because the camera readout frequency of 200 Hz is much lower than the modulator frequency of 50 kHz, the signal delivered by each pixel of the CCD camera array is proportional to the time average hIðtÞ MpðtÞi. Four images corresponding to the four time shifts applied to the modulation MpðtÞ are successively recorded, the signal delivered by each pixel of these four images being

Figure 6 Phase sequencing. Square-wave modulations MpðtÞ are applied to the current supply of the light-emitting diode (LED).

The calculation of the linear combinations Y and Z in Eqs. (15) and (16) give access to the product of the amplitude AS of the wave backscattered by the object and the constant amplitude AR of the wave reflected by the reference mirror. The optical phase can also be obtained [see Eq. (17)].

16

Y ¼ 2ðS3 S1Þ ¼ ASAR sin 1

ð15Þ

16

Z ¼ S0 S1 þ S2 S3 ¼ ASAR cos 2

with

We point out that interference microscopes detect the amplitude of the optical wave reflected by the object rather than its intensity. Intensity images (as produced by a classical microscope) can, of course, be obtained by calculating the squared

amplitude images. An interference microscope can also provide phase images, proportional (modulo =2) to the height between the surface of the object and the surface of the reference mirror [23,24]. Unwrapping the phase images gives a 3D representation of the surface.

In practice, our camera is operated at 200 frames per second (fps). Processed images can thus be produced at the rate of 50 per second. Several images are usually averaged to improve the signal-to-noise ratio (see Section 11.4.4).

Architecture Overview

Optical coherence microscopy hardware and software specifications are tabulated below.

Our design consists of three devices (Fig. 7): an image sensor (camera), a home-made electronic controller (‘‘sequencer’’), and a computer equipped with a frame grabber. To perform the signal detection, the camera is synchronized with the reference frequency by the sequencer. The frame grabber transfers the camera frames into the computer main memory. In real time, the computer performs the linear combinations of frames involved in the ‘‘multiplexed lock-in detection’’ and displays the result. Demodulated images are usually averaged to increase their SNR.

‘‘Multiplexed lock-in detection’’ is a general method used for several physical experiments (see Table 2). Various modulation frequencies, modulation methods, light sources, and cameras are used. Consequently, the system design has to be flexible, and, from this standpoint, several choices are made.

Figure 7 Synchronous imaging kernel architecture. Three devices , two elemental tasks : grab þ processing , one hardware þ software kernel.

Figure 13 Trigger/counter block—Exposure control.

allows synchronization of the EXPOSURE COUNTER and the camera (HSS þ FT periods) (trigger block in Fig. 13). The trigger/counter block also provides a TTL signal used to avoid light flux integration during the HSS period of the camera (i.e., to switch off the light source during HSS).

Finally, the trigger/counter block manages the successive phases of the acquisition process by incrementing the wraparound register (DELAY REGISTER in Fig. 11) each time EXPOSURE COUNTER (Fig. 13) overloads. In addition, it gives a ‘‘first delay value’’ TTL signal that will be checked by the computer subset to synchronize the software part of the SIK design (Section 11.3.4).

As described earlier, the sequencer has to guarantee critical timings of secondary modulation synthesis and camera exposure time. At the same time, the sequencer has to be flexible to match various surrounding devices (Table 2). Flexibility and critical timing are opposite requirements that cannot be easily achieved by a discrete board design. Thus a field programmable gate array (FPGA) programmable logic device has been used in the sequencer design. FPGA integrated circuits realize any kind of digital function (combinatory and/or sequential) according to a program downloaded by the computer through a standard port (e.g., parallel port). Moreover, this reprogrammable architecture offers an easy way to debug.

We designed a motherboard to hold a Xilinx (San Jose, CA) FPGA, a power supply, and several TTL and RS422 buffers. These buffers—connected to the FPGA—allow the sequencer to be easily and quickly upgraded to work with different cameras. A daughter board includes some analog circuits used for primary modulation conditioning and for the PLL multiplier (see generator block discussion) (Fig. 14). Because these subsets belong to a daughter board, the most appropriate technology can be used according to the modulation frequency of the experiment.

Frame Grabbing and Processing (Computer Subset)

Prior to any digital design (hardware and software), data flow rate must be estimated. The CA-D1 maximum frame rate is 203 fps, its frame size is 256 256, and its data format is 8 bit, resulting in about 14 Mbytes/s continuous data flow rate. This data stream is stored in the PC main memory by a frame grabber. Current frame grabbers use a PCI bus, whose maximum bandwidth is 132 Mbytes/s (32 bits at 33 MHz). However, this peak value cannot be obtained in sustained data transfer. For a continuous data stream, 100 Mbytes/s data flow rate is a realistic value. Such frame grabbers are said to be ‘‘real-time,’’ meaning that frames are stored in PC host memory as fast as they are acquired.

Figure 14 Sequencer design implementation. Mother board: XC4003 Xilinx FPGA running up to 100 MHz provides a hardware programmable kernel to the sequencer. The daughter board brings together all application-specific hardware.

The CA-D1 camera is far from reaching the PCI bus bandwidth limit. The remaining available bandwidth is mainly used for the frame processing. Depending on the data treatment, the bandwidth actually needed by the SIK design can be 2, 3, 4, or more times greater. When software load becomes too important, frames are missed.

The data stream is asynchronous with respect to the operating system and the applications that are running on the computer. Avoiding frame misses during the acquisition can be guaranteed on a 100% basis only on real-time operating systems, which is not the case with Microsoft Windows. In fact, the data transfer is made by a device driver running on the computer. The device driver responds to a hardware event, an interrupt, indicating that the data must be moved. Windows does not have deterministic behavior, especially with respect to hardware interrupts. Nevertheless, thanks to the power of current PCs, quasi-deterministic behavior is achieved. In practice, the time determinism of the operating system behavior depends on its total software load (PCI þ CPU).

At this point in the description, each frame grabbed by the computer is anonymous in the multiplexed lock-in detection method. This means that the frames have no relationship to the delay value fixed by the sequencer between the modulation signals. Thus, a ‘‘first delay value’’ synchronization signal is used in the SIK. This signal is provided by the sequencer, and it is checked by a high speed digital port of the computer. This input line can be a generic input/output (I/O) available on the frame grabber or, alternatively, it can be provided by a digital I/O board installed in the computer.