- •Introduction
- •Feature
- •Table of Contents
- •1. Description
- •2. Configuration Summary
- •3. Ordering Information
- •4. Block Diagram
- •5. Pin Configurations
- •5.1. Pin Descriptions
- •5.1.3. Port A (PA[7:0])
- •5.1.4. Port B (PB[3:0])
- •5.1.5. RESET
- •6. I/O Multiplexing
- •7. General Information
- •7.1. Resources
- •7.2. Data Retention
- •7.3. About Code Examples
- •8. AVR CPU Core
- •8.1. Overview
- •8.2. Features
- •8.3. Block Diagram
- •8.4. ALU – Arithmetic Logic Unit
- •8.5. Status Register
- •8.6. General Purpose Register File
- •8.8. Stack Pointer
- •8.10. Instruction Execution Timing
- •8.11. Reset and Interrupt Handling
- •8.11.1. Interrupt Response Time
- •8.12. Register Description
- •8.12.1. Configuration Change Protection Register
- •8.12.2. Stack Pointer Register Low and High byte
- •8.12.3. Status Register
- •9. AVR Memories
- •9.1. Overview
- •9.2. Features
- •9.4. SRAM Data Memory
- •9.4.1. Data Memory Access Times
- •9.5. I/O Memory
- •10. Clock System
- •10.1. Overview
- •10.2. Clock Distribution
- •10.3. Clock Subsystems
- •10.4. Clock Sources
- •10.4.1. Calibrated Internal 8MHz Oscillator
- •10.4.2. External Clock
- •10.4.3. Internal 128kHz Oscillator
- •10.4.4. Switching Clock Source
- •10.4.5. Default Clock Source
- •10.5. System Clock Prescaler
- •10.5.1. Switching Prescaler Setting
- •10.6. Starting
- •10.6.1. Starting from Reset
- •10.6.2. Starting from Power-Down Mode
- •10.6.3. Starting from Idle / ADC Noise Reduction / Standby Mode
- •10.7. Register Description
- •10.7.1. Clock Main Settings Register
- •10.7.2. Oscillator Calibration Register
- •10.7.3. Clock Prescaler Register
- •11. Power Management and Sleep Modes
- •11.1. Overview
- •11.2. Features
- •11.3. Sleep Modes
- •11.3.1. Idle Mode
- •11.3.2. ADC Noise Reduction Mode
- •11.3.4. Standby Mode
- •11.4. Power Reduction Register
- •11.5. Minimizing Power Consumption
- •11.5.1. Analog Comparator
- •11.5.2. Analog to Digital Converter
- •11.5.3. Internal Voltage Reference
- •11.5.4. Watchdog Timer
- •11.5.5. Port Pins
- •11.6. Register Description
- •11.6.1. Sleep Mode Control Register
- •11.6.2. Power Reduction Register
- •12. SCRST - System Control and Reset
- •12.1. Overview
- •12.2. Features
- •12.3. Resetting the AVR
- •12.4. Reset Sources
- •12.4.3. External Reset
- •12.4.4. Watchdog System Reset
- •12.5. Watchdog Timer
- •12.5.1. Overview
- •12.5.2. Procedure for Changing the Watchdog Timer Configuration
- •12.5.2.1. Safety Level 1
- •12.5.2.2. Safety Level 2
- •12.5.3. Code Examples
- •12.6. Register Description
- •12.6.1. Watchdog Timer Control Register
- •12.6.2. VCC Level Monitoring Control and Status register
- •12.6.3. Reset Flag Register
- •13. Interrupts
- •13.1. Overview
- •13.2. Interrupt Vectors
- •13.3. External Interrupts
- •13.3.1. Low Level Interrupt
- •13.3.2. Pin Change Interrupt Timing
- •13.4. Register Description
- •13.4.1. External Interrupt Control Register A
- •13.4.2. External Interrupt Mask Register
- •13.4.3. External Interrupt Flag Register
- •13.4.4. Pin Change Interrupt Control Register
- •13.4.5. Pin Change Interrupt Flag Register
- •13.4.6. Pin Change Mask Register 0
- •13.4.7. Pin Change Mask Register 1
- •14. I/O-Ports
- •14.1. Overview
- •14.2. Features
- •14.3. I/O Pin Equivalent Schematic
- •14.4. Ports as General Digital I/O
- •14.4.1. Configuring the Pin
- •14.4.2. Toggling the Pin
- •14.4.4. Reading the Pin Value
- •14.4.5. Digital Input Enable and Sleep Modes
- •14.4.6. Unconnected Pins
- •14.4.7. Program Example
- •14.4.8. Alternate Port Functions
- •14.4.8.1. Alternate Functions of Port A
- •14.4.8.2. Alternate Functions of Port B
- •14.5. Register Description
- •14.5.1. Port A Input Pins Address
- •14.5.2. Port A Data Direction Register
- •14.5.3. Port A Data Register
- •14.5.5. Port B Input Pins Address
- •14.5.6. Port B Data Direction Register
- •14.5.7. Port B Data Register
- •14.5.9. Port Control Register
- •15. USART - Universal Synchronous Asynchronous Receiver Transceiver
- •15.1. Overview
- •15.2. Features
- •15.3. Block Diagram
- •15.4. Clock Generation
- •15.4.1. Internal Clock Generation – The Baud Rate Generator
- •15.4.2. Double Speed Operation (U2X0)
- •15.4.3. External Clock
- •15.4.4. Synchronous Clock Operation
- •15.5. Frame Formats
- •15.5.1. Parity Bit Calculation
- •15.6. USART Initialization
- •15.7. Data Transmission – The USART Transmitter
- •15.7.1. Sending Frames with 5 to 8 Data Bits
- •15.7.2. Sending Frames with 9 Data Bit
- •15.7.3. Transmitter Flags and Interrupts
- •15.7.4. Parity Generator
- •15.7.5. Disabling the Transmitter
- •15.8. Data Reception – The USART Receiver
- •15.8.1. Receiving Frames with 5 to 8 Data Bits
- •15.8.2. Receiving Frames with 9 Data Bits
- •15.8.3. Receive Compete Flag and Interrupt
- •15.8.4. Receiver Error Flags
- •15.8.5. Parity Checker
- •15.8.6. Disabling the Receiver
- •15.8.7. Flushing the Receive Buffer
- •15.9. Asynchronous Data Reception
- •15.9.1. Asynchronous Clock Recovery
- •15.9.2. Asynchronous Data Recovery
- •15.9.3. Asynchronous Operational Range
- •15.9.4. Start Frame Detection
- •15.10. Multi-Processor Communication Mode
- •15.10.1. Using MPCMn
- •15.11. Examples of Baud Rate Setting
- •15.12. Register Description
- •15.12.1. USART I/O Data Register 0
- •15.12.2. USART Control and Status Register 0 A
- •15.12.3. USART Control and Status Register 0 B
- •15.12.4. USART Control and Status Register 0 C
- •15.12.5. USART Control and Status Register 0 D
- •15.12.6. USART Baud Rate 0 Register Low and High byte
- •16. USARTSPI - USART in SPI Mode
- •16.1. Overview
- •16.2. Features
- •16.3. Clock Generation
- •16.4. SPI Data Modes and Timing
- •16.5. Frame Formats
- •16.5.1. USART MSPIM Initialization
- •16.6. Data Transfer
- •16.6.1. Transmitter and Receiver Flags and Interrupts
- •16.6.2. Disabling the Transmitter or Receiver
- •16.7. AVR USART MSPIM vs. AVR SPI
- •16.8. Register Description
- •17.1. Overview
- •17.2. Features
- •17.3. Block Diagram
- •17.4. Definitions
- •17.5. Registers
- •17.6.1. Reusing the Temporary High Byte Register
- •17.7. Timer/Counter Clock Sources
- •17.7.1. Internal Clock Source - Prescaler
- •17.7.2. Prescaler Reset
- •17.7.3. External Clock Source
- •17.8. Counter Unit
- •17.9. Input Capture Unit
- •17.9.1. Input Capture Trigger Source
- •17.9.2. Noise Canceler
- •17.9.3. Using the Input Capture Unit
- •17.10. Output Compare Units
- •17.10.1. Force Output Compare
- •17.10.2. Compare Match Blocking by TCNT0 Write
- •17.10.3. Using the Output Compare Unit
- •17.11. Compare Match Output Unit
- •17.11.1. Compare Output Mode and Waveform Generation
- •17.12. Modes of Operation
- •17.12.1. Normal Mode
- •17.12.2. Clear Timer on Compare Match (CTC) Mode
- •17.12.3. Fast PWM Mode
- •17.12.4. Phase Correct PWM Mode
- •17.12.5. Phase and Frequency Correct PWM Mode
- •17.13. Timer/Counter Timing Diagrams
- •17.14. Register Description
- •17.14.1. Timer/Counter0 Control Register A
- •17.14.2. Timer/Counter0 Control Register B
- •17.14.3. Timer/Counter0 Control Register C
- •17.14.4. Timer/Counter 0 Low and High byte
- •17.14.5. Output Comparte Register A 0 Low and High byte
- •17.14.6. Output Comparte Register B 0 Low and High byte
- •17.14.7. Input Capture Register 0 Low and High byte
- •17.14.8. Timer/Counter0 Interrupt Mask Register
- •17.14.9. Timer/Counter0 Interrupt Flag Register
- •17.14.10. General Timer/Counter Control Register
- •18. AC - Analog Comparator
- •18.1. Overview
- •18.2. Features
- •18.3. Block Diagram
- •18.4. Register Description
- •18.4.1. Analog Comparator Control and Status Register
- •18.4.2. Analog Comparator Control and Status Register 0
- •18.4.3. Digital Input Disable Register 0
- •19. ADC - Analog to Digital Converter
- •19.1. Overview
- •19.2. Features
- •19.3. Block Diagram
- •19.4. Operation
- •19.5. Starting a Conversion
- •19.6. Prescaling and Conversion Timing
- •19.7. Changing Channel or Reference Selection
- •19.8. ADC Input Channels
- •19.9. ADC Voltage Reference
- •19.10. ADC Noise Canceler
- •19.11. Analog Input Circuitry
- •19.12. Analog Noise Canceling Techniques
- •19.13. ADC Accuracy Definitions
- •19.14. ADC Conversion Result
- •19.15. Register Description
- •19.15.1. ADC Multiplexer Selection Register
- •19.15.2. ADC Control and Status Register A
- •19.15.3. ADC Control and Status Register B
- •19.15.4. ADC Data Register Low and High Byte (ADLAR=0)
- •19.15.5. ADC Data Register Low and High Byte (ADLAR=1)
- •19.15.6. Digital Input Disable Register 0
- •20.1. Overview
- •20.2. Features
- •20.3.2. Flash Memory
- •20.3.3. Configuration Section
- •20.3.3.1. Latching of Configuration Bits
- •20.3.4. Signature Section
- •20.3.4.1. Signature Row Summary
- •20.3.4.1.1. Device ID n
- •20.3.4.1.2. Serial Number Byte n
- •20.3.5. Calibration Section
- •20.4. Accessing the NVM
- •20.4.1. Addressing the Flash
- •20.4.2. Reading the Flash
- •20.4.3. Programming the Flash
- •20.4.3.1. Chip Erase
- •20.4.3.2. Erasing the Code Section
- •20.4.3.3. Writing a Code Word
- •20.4.3.4. Erasing the Configuration Section
- •20.4.3.5. Writing a Configuration Word
- •20.4.4. Reading NVM Lock Bits
- •20.4.5. Writing NVM Lock Bits
- •20.5. Self programming
- •20.6. External Programming
- •20.6.1. Entering External Programming Mode
- •20.6.2. Exiting External Programming Mode
- •20.7. Register Description
- •21.1. Overview
- •21.2. Features
- •21.3. Block Diagram
- •21.4. Physical Layer of Tiny Programming Interface
- •21.4.1. Enabling
- •21.4.2. Disabling
- •21.4.3. Frame Format
- •21.4.4. Parity Bit Calculation
- •21.4.5. Supported Characters
- •21.4.6. Operation
- •21.4.7. Serial Data Reception
- •21.4.8. Serial Data Transmission
- •21.4.9. Collision Detection Exception
- •21.4.10. Direction Change
- •21.4.11. Access Layer of Tiny Programming Interface
- •21.4.11.1. Message format
- •21.4.11.2. Exception Handling and Synchronisation
- •21.5. Instruction Set
- •21.5.1. SLD - Serial LoaD from data space using indirect addressing
- •21.5.2. SST - Serial STore to data space using indirect addressing
- •21.5.3. SSTPR - Serial STore to Pointer Register
- •21.5.4. SIN - Serial IN from i/o space using direct addressing
- •21.5.5. SOUT - Serial OUT to i/o space using direct addressing
- •21.5.6. SLDCS - Serial LoaD data from Control and Status space using direct addressing
- •21.5.7. SSTCS - Serial STore data to Control and Status space using direct addressing
- •21.5.8. SKEY - Serial KEY signaling
- •21.7. Control and Status Space Register Descriptions
- •21.7.1. Tiny Programming Interface Identification Register
- •21.7.2. Tiny Programming Interface Physical Layer Control Register
- •21.7.3. Tiny Programming Interface Status Register
- •22. Electrical Characteristics
- •22.1. Absolute Maximum Ratings*
- •22.2. DC Characteristics
- •22.3. Speed
- •22.4. Clock Characteristics
- •22.4.1. Accuracy of Calibrated Internal Oscillator
- •22.4.2. External Clock Drive
- •22.5. System and Reset Characteristics
- •22.6. Analog Comparator Characteristics
- •22.7. ADC Characteristics
- •22.8. Serial Programming Characteristics
- •23. Typical Characteristics
- •23.1. Active Supply Current
- •23.2. Idle Supply Current
- •23.3. Supply Current of I/O Modules
- •23.5. Pin Driver Strength
- •23.6. Pin Threshold and Hysteresis
- •23.7. Analog Comparator Offset
- •23.9. Internal Oscillator Speed
- •23.10. VLM Thresholds
- •23.11. Current Consumption of Peripheral Units
- •23.12. Current Consumption in Reset and Reset Pulsewidth
- •24. Register Summary
- •24.1. Note
- •25. Instruction Set Summary
- •26. Packaging Information
- •27. Errata
- •27.1. ATtiny102
- •27.2. ATtiny104
- •28. Datasheet Revision History
25.Instruction Set Summary
Table 24-1. Arithmetic and Logic Instructions
Mnemonic |
Operands |
Description |
|
Op |
|
Flags |
#Clocks |
|
|
AVRrc |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ADD |
Rd, Rr |
Add without Carry |
Rd |
← |
Rd + Rr |
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
ADC |
Rd, Rr |
Add with Carry |
Rd |
← |
Rd + Rr + C |
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
ADIW |
Rd, K |
Add Immediate to Word |
Rd |
← |
Rd + 1:Rd + K |
Z,C,N,V,S |
N/A |
|
|
|
|
|
|
|
|
SUB |
Rd, Rr |
Subtract without Carry |
Rd |
← |
Rd - Rr |
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
SUBI |
Rd, K |
Subtract Immediate |
Rd |
← |
Rd - K |
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
SBC |
Rd, Rr |
Subtract with Carry |
Rd |
← |
Rd - Rr - C |
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
SBCI |
Rd, K |
Subtract Immediate with Carry |
Rd |
← |
Rd - K - C |
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
SBIW |
Rd, K |
Subtract Immediate from Word |
Rd + 1:Rd |
← |
Rd + 1:Rd - K |
Z,C,N,V,S |
N/A |
|
|
|
|
|
|
|
|
AND |
Rd, Rr |
Logical AND |
Rd |
← |
Rd • Rr |
Z,N,V,S |
1 |
|
|
|
|
|
|
|
|
ANDI |
Rd, K |
Logical AND with Immediate |
Rd |
← |
Rd • K |
Z,N,V,S |
1 |
|
|
|
|
|
|
|
|
OR |
Rd, Rr |
Logical OR |
Rd |
← |
Rd v Rr |
Z,N,V,S |
1 |
|
|
|
|
|
|
|
|
ORI |
Rd, K |
Logical OR with Immediate |
Rd |
← |
Rd v K |
Z,N,V,S |
1 |
|
|
|
|
|
|
|
|
EOR |
Rd, Rr |
Exclusive OR |
Rd |
← |
Rd Rr |
Z,N,V,S |
1 |
COM |
Rd |
One’s Complement |
Rd |
← |
$FF - Rd |
Z,C,N,V,S |
1 |
|
|
|
|
|
|
|
|
NEG |
Rd |
Two’s Complement |
Rd |
← |
$00 - Rd |
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
SBR |
Rd,K |
Set Bit(s) in Register |
Rd |
← |
Rd v K |
Z,N,V,S |
1 |
|
|
|
|
|
|
|
|
CBR |
Rd,K |
Clear Bit(s) in Register |
Rd |
← |
Rd • ($FFh - K) |
Z,N,V,S |
1 |
|
|
|
|
|
|
|
|
INC |
Rd |
Increment |
Rd |
← |
Rd + 1 |
Z,N,V,S |
1 |
|
|
|
|
|
|
|
|
DEC |
Rd |
Decrement |
Rd |
← |
Rd - 1 |
Z,N,V,S |
1 |
|
|
|
|
|
|
|
|
TST |
Rd |
Test for Zero or Minus |
Rd |
← |
Rd • Rd |
Z,N,V,S |
1 |
|
|
|
|
|
|
|
|
CLR |
Rd |
Clear Register |
Rd |
← |
Rd Rd |
Z,N,V,S |
1 |
SER |
Rd |
Set Register |
Rd |
← |
$FF |
None |
1 |
|
|
|
|
|
|
|
|
Table 24-2. Branch Instructions
Mnemonic |
Operands |
Description |
|
Op |
|
Flags |
#Clocks |
|
|
AVRrc |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RJMP |
k |
Relative Jump |
PC |
← |
PC + k + 1 |
None |
2 |
|
|
|
|
|
|
|
|
IJMP |
|
Indirect Jump to (Z) |
PC(15:0) |
← |
Z |
None |
2 |
|
|
|
PC(21:16) |
← |
0 |
|
|
|
|
|
|
|
|
|
|
RCALL |
k |
Relative Call Subroutine |
PC |
← |
PC + k + 1 |
None |
3(1) |
ICALL |
|
Indirect Call to (Z) |
PC(15:0) |
← |
Z |
None |
3(1) |
|
|
|
PC(21:16) |
← |
0 |
|
|
|
|
|
|
|
|
|
|
RET |
|
Subroutine Return |
PC |
← |
STACK |
None |
6(1) |
RETI |
|
Interrupt Return |
PC |
← |
STACK |
I |
6(1) |
CPSE |
Rd,Rr |
Compare, Skip if Equal |
if (Rd = Rr) PC |
← |
PC + 2 or 3 |
None |
1 / 2 |
|
|
|
|
|
|
|
|
CP |
Rd,Rr |
Compare |
Rd - Rr |
|
|
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
CPC |
Rd,Rr |
Compare with Carry |
Rd - Rr - C |
|
|
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
CPI |
Rd,K |
Compare with Immediate |
Rd - K |
|
|
Z,C,N,V,S,H |
1 |
|
|
|
|
|
|
|
|
Atmel ATtiny102 / ATtiny104 [DATASHEET] 246
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Mnemonic |
Operands |
Description |
|
Op |
|
Flags |
#Clocks |
|
|
|
|
AVRrc |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SBRC |
Rr, b |
Skip if Bit in Register Cleared |
if (Rr(b) = 0) PC |
← |
PC + 2 or 3 |
None |
1 / 2 |
|
|
|
|
|
|
|
|
|
|
|
|
SBRS |
Rr, b |
Skip if Bit in Register Set |
if (Rr(b) = 1) PC |
← |
PC + 2 or 3 |
None |
1 / 2 |
|
|
|
|
|
|
|
|
|
|
|
|
SBIC |
A, b |
Skip if Bit in I/O Register Cleared |
if (I/O(A,b) = 0) PC |
← |
PC + 2 or 3 |
None |
1 / 2 |
|
|
|
|
|
|
|
|
|
|
|
|
SBIS |
A, b |
Skip if Bit in I/O Register Set |
If (I/O(A,b) =1) PC |
← |
PC + 2 or 3 |
None |
1 / 2 |
|
|
|
|
|
|
|
|
|
|
|
|
BRBS |
s, k |
Branch if Status Flag Set |
if (SREG(s) = 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
|
|
|
|
|
|
|
|
|
|
|
|
BRBC |
s, k |
Branch if Status Flag Cleared |
if (SREG(s) = 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
|
|
|
|
|
|
|
|
|
|
|
|
BREQ |
k |
Branch if Equal |
if (Z = 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
|
|
|
|
|
|
|
|
|
|
|
|
BRNE |
k |
Branch if Not Equal |
if (Z = 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
|
|
|
|
|
|
|
|
|
|
|
|
BRCS |
k |
Branch if Carry Set |
if (C = 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRCC |
k |
Branch if Carry Cleared |
if (C = 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRSH |
k |
Branch if Same or Higher |
if (C = 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRLO |
k |
Branch if Lower |
if (C = 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRMI |
k |
Branch if Minus |
if (N = 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRPL |
k |
Branch if Plus |
if (N = 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRGE |
k |
Branch if Greater or Equal, Signed |
if (N V= 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
|
|
BRLT |
k |
Branch if Less Than, Signed |
if (N V= 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
|
|
BRHS |
k |
Branch if Half Carry Flag Set |
if (H = 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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|
|
BRHC |
k |
Branch if Half Carry Flag Cleared |
if (H = 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRTS |
k |
Branch if T Flag Set |
if (T = 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRTC |
k |
Branch if T Flag Cleared |
if (T = 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRVS |
k |
Branch if Overflow Flag is Set |
if (V = 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRVC |
k |
Branch if Overflow Flag is Cleared |
if (V = 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRIE |
k |
Branch if Interrupt Enabled |
if (I = 1) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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BRID |
k |
Branch if Interrupt Disabled |
if (I = 0) then PC |
← |
PC + k + 1 |
None |
1 / 2 |
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Table 24-3. Data Transfer Instructions
Mnemonic |
Operands |
Description |
|
Op |
|
Flags |
#Clocks |
|
|
AVRrc |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MOV |
Rd, Rr |
Copy Register |
Rd |
← |
Rr |
None |
1 |
|
|
|
|
|
|
|
|
LDI |
Rd, K |
Load Immediate |
Rd |
← |
K |
None |
1 |
|
|
|
|
|
|
|
|
LDS |
Rd, k |
Load Direct from data space |
Rd |
← |
(k) |
None |
2 |
|
|
|
|
|
|
|
|
LD |
Rd, X |
Load Indirect |
Rd |
← |
(X) |
None |
1 / 2 |
|
|
|
|
|
|
|
|
LD |
Rd, X+ |
Load Indirect and Post-Increment |
Rd |
← |
(X) |
None |
2 / 3 |
|
|
|
X |
← |
X + 1 |
|
|
|
|
|
|
|
|
|
|
LD |
Rd, -X |
Load Indirect and Pre-Decrement |
X |
← |
X - 1 |
None |
2 / 3 |
|
|
|
Rd |
← |
(X) |
|
|
|
|
|
|
|
|
|
|
LD |
Rd, Y |
Load Indirect |
Rd |
← |
(Y) |
None |
1 / 2 |
|
|
|
|
|
|
|
|
LD |
Rd, Y+ |
Load Indirect and Post-Increment |
Rd |
← |
(Y) |
None |
2 / 3 |
|
|
|
Y |
← |
Y + 1 |
|
|
|
|
|
|
|
|
|
|
LD |
Rd, -Y |
Load Indirect and Pre-Decrement |
Y |
← |
Y - 1 |
None |
2 / 3 |
|
|
|
Rd |
← |
(Y) |
|
|
|
|
|
|
|
|
|
|
Atmel ATtiny102 / ATtiny104 [DATASHEET] 247
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
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|
|
|
Mnemonic |
Operands |
Description |
|
Op |
|
Flags |
#Clocks |
|
|
|
|
AVRrc |
|
|||||
|
|
|
|
|
|
|
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|
|
LDD |
Rd, Y+q |
Load Indirect with Displacement |
Rd |
← |
(Y + q) |
None |
N/A |
|
|
|
|
|
|
|
|
|
|
|
|
LD |
Rd, Z |
Load Indirect |
Rd |
← |
(Z) |
None |
1 / 2 |
|
|
|
|
|
|
|
|
|
|
|
|
LD |
Rd, Z+ |
Load Indirect and Post-Increment |
Rd |
← |
(Z) |
None |
2 / 3 |
|
|
|
|
|
Z |
← |
Z+1 |
|
|
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|
LD |
Rd, -Z |
Load Indirect and Pre-Decrement |
Z |
← |
Z - 1 |
None |
2 / 3 |
|
|
|
|
|
Rd |
← |
(Z) |
|
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|
LDD |
Rd, Z+q |
Load Indirect with Displacement |
Rd |
← |
(Z + q) |
None |
N/A |
|
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|
|
STS |
k, Rr |
Store Direct to Data Space |
(k) |
← |
Rd |
None |
1 |
|
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|
|
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|
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|
|
|
ST |
X, Rr |
Store Indirect |
(X) |
← |
Rr |
None |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
ST |
X+, Rr |
Store Indirect and Post-Increment |
(X) |
← |
Rr |
None |
1 |
|
|
|
|
|
X |
← |
X + 1 |
|
|
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|
|
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|
|
|
|
ST |
-X, Rr |
Store Indirect and Pre-Decrement |
X |
← |
X - 1 |
None |
2 |
|
|
|
|
|
(X) |
← |
Rr |
|
|
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|
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|
|
ST |
Y, Rr |
Store Indirect |
(Y) |
← |
Rr |
None |
1 |
|
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|
|
|
|
|
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|
|
|
ST |
Y+, Rr |
Store Indirect and Post-Increment |
(Y) |
← |
Rr |
None |
1 |
|
|
|
|
|
Y |
← |
Y + 1 |
|
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|
|
ST |
-Y, Rr |
Store Indirect and Pre-Decrement |
Y |
← |
Y - 1 |
None |
2 |
|
|
|
|
|
(Y) |
← |
Rr |
|
|
|
|
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|
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|
|
|
STD |
Y+q, Rr |
Store Indirect with Displacement |
(Y + q) |
← |
Rr |
None |
N/A |
|
|
|
|
|
|
|
|
|
|
|
|
ST |
Z, Rr |
Store Indirect |
(Z) |
← |
Rr |
None |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
ST |
Z+, Rr |
Store Indirect and Post-Increment |
(Z) |
← |
Rr |
None |
1 |
|
|
|
|
|
Z |
← |
Z + 1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ST |
-Z, Rr |
Store Indirect and Pre-Decrement |
Z |
← |
Z - 1 |
None |
2 |
|
|
|
|
|
|
|
|
|
|
|
|
STD |
Z+q,Rr |
Store Indirect with Displacement |
(Z + q) |
← |
Rr |
None |
N/A |
|
|
|
|
|
|
|
|
|
|
|
|
LPM |
|
Load Program Memory |
R0 |
← |
(Z) |
None |
N/A |
|
|
|
|
|
|
|
|
|
|
|
|
IN |
Rd, A |
In From I/O Location |
Rd |
← |
I/O(A) |
None |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
OUT |
A, Rr |
Out To I/O Location |
I/O(A) |
← |
Rr |
None |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
PUSH |
Rr |
Push Register on Stack |
STACK |
← |
Rr |
None |
1(1) |
|
|
POP |
Rd |
Pop Register from Stack |
Rd |
← |
STACK |
None |
3(1) |
|
Table 24-4. Bit and Bit-test Instructions
Mnemonic |
Operands |
Description |
|
Op |
|
Flags |
#Clocks |
|
|
AVRrc |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LSL |
Rd |
Logical Shift Left |
Rd(n+1) |
← |
Rd(n) |
Z,C,N,V,H |
1 |
|
|
|
Rd(0) |
← |
0 |
|
|
|
|
|
C |
← |
Rd(7) |
|
|
|
|
|
|
|
|
|
|
LSR |
Rd |
Logical Shift Right |
Rd(n) |
← |
Rd(n+1) |
Z,C,N,V |
1 |
|
|
|
Rd(7) |
← |
0 |
|
|
|
|
|
C |
← |
Rd(0) |
|
|
|
|
|
|
|
|
|
|
ROL |
Rd |
Rotate Left Through Carry |
Rd(0) |
← |
C |
Z,C,N,V,H |
1 |
|
|
|
Rd(n+1) |
← |
Rd(n) |
|
|
|
|
|
C |
← |
Rd(7) |
|
|
|
|
|
|
|
|
|
|
Atmel ATtiny102 / ATtiny104 [DATASHEET] 248
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
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|
|
Mnemonic |
Operands |
Description |
|
Op |
|
Flags |
#Clocks |
|
|
|
|
AVRrc |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ROR |
Rd |
Rotate Right Through Carry |
Rd(7) |
← |
C |
Z,C,N,V |
1 |
|
|
|
|
|
Rd(n) |
← |
Rd(n+1) |
|
|
|
|
|
|
|
C |
← |
Rd(0) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ASR |
Rd |
Arithmetic Shift Right |
Rd(n) |
← |
Rd(n+1), n=0..6 |
Z,C,N,V |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SWAP |
Rd |
Swap Nibbles |
Rd(3..0) |
↔ |
Rd(7..4) |
None |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SBI |
A, b |
Set Bit in I/O Register |
I/O(A, b) |
← |
1 |
None |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
CBI |
A, b |
Clear Bit in I/O Register |
I/O(A, b) |
← |
0 |
None |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
BST |
Rr, b |
Bit Store from Register to T |
T |
← |
Rr(b) |
T |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
BLD |
Rd, b |
Bit load from T to Register |
Rd(b) |
← |
T |
None |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
BSET |
s |
Flag Set |
SREG(s) |
← |
1 |
SREG(s) |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
BCLR |
s |
Flag Clear |
SREG(s) |
← |
0 |
SREG(s) |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SEC |
|
Set Carry |
C |
← |
1 |
C |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
CLC |
|
Clear Carry |
C |
← |
0 |
C |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SEN |
|
Set Negative Flag |
N |
← |
1 |
N |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
CLN |
|
Clear Negative Flag |
N |
← |
0 |
N |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SEZ |
|
Set Zero Flag |
Z |
← |
1 |
Z |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
CLZ |
|
Clear Zero Flag |
Z |
← |
0 |
Z |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SEI |
|
Global Interrupt Enable |
I |
← |
1 |
I |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
CLI |
|
Global Interrupt Disable |
I |
← |
0 |
I |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SES |
|
Set Signed Test Flag |
S |
← |
1 |
S |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
CLS |
|
Clear Signed Test Flag |
S |
← |
0 |
S |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SEV |
|
Set Two’s Complement Overflow |
V |
← |
1 |
V |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
CLV |
|
Clear Two’s Complement Overflow |
V |
← |
0 |
V |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SET |
|
Set T in SREG |
T |
← |
1 |
T |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
CLT |
|
Clear T in SREG |
T |
← |
0 |
T |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
SEH |
|
Set Half Carry Flag in SREG |
H |
← |
1 |
H |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
CLH |
|
Clear Half Carry Flag in SREG |
H |
← |
0 |
H |
1 |
|
|
|
|
|
|
|
|
|
|
|
Table 24-5. MCU Control Instructions
Mnemonic |
Operands |
Description |
Operation |
Flags |
#Clocks |
|
AVRrc |
||||||
|
|
|
|
|
||
|
|
|
|
|
|
|
BREAK |
|
Break |
(See also in Debug interface description) |
None |
1 |
|
|
|
|
|
|
|
|
NOP |
|
No Operation |
|
None |
1 |
|
|
|
|
|
|
|
|
SLEEP |
|
Sleep |
(see also power management and sleep description) |
None |
1 |
|
|
|
|
|
|
|
|
WDR |
|
Watchdog Reset |
(see also Watchdog Controller description) |
None |
1 |
|
|
|
|
|
|
|
Note:
1.Cycle time for data memory accesses assume internal RAM access, and are not valid for accesses through the NVM controller. A minimum of one extra cycle must be added when accessing memory through the NVM controller (such as Flash and EEPROM), but depending on simultaneous accesses by other masters or the NVM controller state, there may be more than one extra cycle.
Atmel ATtiny102 / ATtiny104 [DATASHEET] 249
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016