- •Introduction
- •Feature
- •Table of Contents
- •1. Description
- •2. Configuration Summary
- •3. Ordering Information
- •4. Block Diagram
- •5. Pin Configurations
- •5.1. Pin Descriptions
- •5.1.3. Port A (PA[7:0])
- •5.1.4. Port B (PB[3:0])
- •5.1.5. RESET
- •6. I/O Multiplexing
- •7. General Information
- •7.1. Resources
- •7.2. Data Retention
- •7.3. About Code Examples
- •8. AVR CPU Core
- •8.1. Overview
- •8.2. Features
- •8.3. Block Diagram
- •8.4. ALU – Arithmetic Logic Unit
- •8.5. Status Register
- •8.6. General Purpose Register File
- •8.8. Stack Pointer
- •8.10. Instruction Execution Timing
- •8.11. Reset and Interrupt Handling
- •8.11.1. Interrupt Response Time
- •8.12. Register Description
- •8.12.1. Configuration Change Protection Register
- •8.12.2. Stack Pointer Register Low and High byte
- •8.12.3. Status Register
- •9. AVR Memories
- •9.1. Overview
- •9.2. Features
- •9.4. SRAM Data Memory
- •9.4.1. Data Memory Access Times
- •9.5. I/O Memory
- •10. Clock System
- •10.1. Overview
- •10.2. Clock Distribution
- •10.3. Clock Subsystems
- •10.4. Clock Sources
- •10.4.1. Calibrated Internal 8MHz Oscillator
- •10.4.2. External Clock
- •10.4.3. Internal 128kHz Oscillator
- •10.4.4. Switching Clock Source
- •10.4.5. Default Clock Source
- •10.5. System Clock Prescaler
- •10.5.1. Switching Prescaler Setting
- •10.6. Starting
- •10.6.1. Starting from Reset
- •10.6.2. Starting from Power-Down Mode
- •10.6.3. Starting from Idle / ADC Noise Reduction / Standby Mode
- •10.7. Register Description
- •10.7.1. Clock Main Settings Register
- •10.7.2. Oscillator Calibration Register
- •10.7.3. Clock Prescaler Register
- •11. Power Management and Sleep Modes
- •11.1. Overview
- •11.2. Features
- •11.3. Sleep Modes
- •11.3.1. Idle Mode
- •11.3.2. ADC Noise Reduction Mode
- •11.3.4. Standby Mode
- •11.4. Power Reduction Register
- •11.5. Minimizing Power Consumption
- •11.5.1. Analog Comparator
- •11.5.2. Analog to Digital Converter
- •11.5.3. Internal Voltage Reference
- •11.5.4. Watchdog Timer
- •11.5.5. Port Pins
- •11.6. Register Description
- •11.6.1. Sleep Mode Control Register
- •11.6.2. Power Reduction Register
- •12. SCRST - System Control and Reset
- •12.1. Overview
- •12.2. Features
- •12.3. Resetting the AVR
- •12.4. Reset Sources
- •12.4.3. External Reset
- •12.4.4. Watchdog System Reset
- •12.5. Watchdog Timer
- •12.5.1. Overview
- •12.5.2. Procedure for Changing the Watchdog Timer Configuration
- •12.5.2.1. Safety Level 1
- •12.5.2.2. Safety Level 2
- •12.5.3. Code Examples
- •12.6. Register Description
- •12.6.1. Watchdog Timer Control Register
- •12.6.2. VCC Level Monitoring Control and Status register
- •12.6.3. Reset Flag Register
- •13. Interrupts
- •13.1. Overview
- •13.2. Interrupt Vectors
- •13.3. External Interrupts
- •13.3.1. Low Level Interrupt
- •13.3.2. Pin Change Interrupt Timing
- •13.4. Register Description
- •13.4.1. External Interrupt Control Register A
- •13.4.2. External Interrupt Mask Register
- •13.4.3. External Interrupt Flag Register
- •13.4.4. Pin Change Interrupt Control Register
- •13.4.5. Pin Change Interrupt Flag Register
- •13.4.6. Pin Change Mask Register 0
- •13.4.7. Pin Change Mask Register 1
- •14. I/O-Ports
- •14.1. Overview
- •14.2. Features
- •14.3. I/O Pin Equivalent Schematic
- •14.4. Ports as General Digital I/O
- •14.4.1. Configuring the Pin
- •14.4.2. Toggling the Pin
- •14.4.4. Reading the Pin Value
- •14.4.5. Digital Input Enable and Sleep Modes
- •14.4.6. Unconnected Pins
- •14.4.7. Program Example
- •14.4.8. Alternate Port Functions
- •14.4.8.1. Alternate Functions of Port A
- •14.4.8.2. Alternate Functions of Port B
- •14.5. Register Description
- •14.5.1. Port A Input Pins Address
- •14.5.2. Port A Data Direction Register
- •14.5.3. Port A Data Register
- •14.5.5. Port B Input Pins Address
- •14.5.6. Port B Data Direction Register
- •14.5.7. Port B Data Register
- •14.5.9. Port Control Register
- •15. USART - Universal Synchronous Asynchronous Receiver Transceiver
- •15.1. Overview
- •15.2. Features
- •15.3. Block Diagram
- •15.4. Clock Generation
- •15.4.1. Internal Clock Generation – The Baud Rate Generator
- •15.4.2. Double Speed Operation (U2X0)
- •15.4.3. External Clock
- •15.4.4. Synchronous Clock Operation
- •15.5. Frame Formats
- •15.5.1. Parity Bit Calculation
- •15.6. USART Initialization
- •15.7. Data Transmission – The USART Transmitter
- •15.7.1. Sending Frames with 5 to 8 Data Bits
- •15.7.2. Sending Frames with 9 Data Bit
- •15.7.3. Transmitter Flags and Interrupts
- •15.7.4. Parity Generator
- •15.7.5. Disabling the Transmitter
- •15.8. Data Reception – The USART Receiver
- •15.8.1. Receiving Frames with 5 to 8 Data Bits
- •15.8.2. Receiving Frames with 9 Data Bits
- •15.8.3. Receive Compete Flag and Interrupt
- •15.8.4. Receiver Error Flags
- •15.8.5. Parity Checker
- •15.8.6. Disabling the Receiver
- •15.8.7. Flushing the Receive Buffer
- •15.9. Asynchronous Data Reception
- •15.9.1. Asynchronous Clock Recovery
- •15.9.2. Asynchronous Data Recovery
- •15.9.3. Asynchronous Operational Range
- •15.9.4. Start Frame Detection
- •15.10. Multi-Processor Communication Mode
- •15.10.1. Using MPCMn
- •15.11. Examples of Baud Rate Setting
- •15.12. Register Description
- •15.12.1. USART I/O Data Register 0
- •15.12.2. USART Control and Status Register 0 A
- •15.12.3. USART Control and Status Register 0 B
- •15.12.4. USART Control and Status Register 0 C
- •15.12.5. USART Control and Status Register 0 D
- •15.12.6. USART Baud Rate 0 Register Low and High byte
- •16. USARTSPI - USART in SPI Mode
- •16.1. Overview
- •16.2. Features
- •16.3. Clock Generation
- •16.4. SPI Data Modes and Timing
- •16.5. Frame Formats
- •16.5.1. USART MSPIM Initialization
- •16.6. Data Transfer
- •16.6.1. Transmitter and Receiver Flags and Interrupts
- •16.6.2. Disabling the Transmitter or Receiver
- •16.7. AVR USART MSPIM vs. AVR SPI
- •16.8. Register Description
- •17.1. Overview
- •17.2. Features
- •17.3. Block Diagram
- •17.4. Definitions
- •17.5. Registers
- •17.6.1. Reusing the Temporary High Byte Register
- •17.7. Timer/Counter Clock Sources
- •17.7.1. Internal Clock Source - Prescaler
- •17.7.2. Prescaler Reset
- •17.7.3. External Clock Source
- •17.8. Counter Unit
- •17.9. Input Capture Unit
- •17.9.1. Input Capture Trigger Source
- •17.9.2. Noise Canceler
- •17.9.3. Using the Input Capture Unit
- •17.10. Output Compare Units
- •17.10.1. Force Output Compare
- •17.10.2. Compare Match Blocking by TCNT0 Write
- •17.10.3. Using the Output Compare Unit
- •17.11. Compare Match Output Unit
- •17.11.1. Compare Output Mode and Waveform Generation
- •17.12. Modes of Operation
- •17.12.1. Normal Mode
- •17.12.2. Clear Timer on Compare Match (CTC) Mode
- •17.12.3. Fast PWM Mode
- •17.12.4. Phase Correct PWM Mode
- •17.12.5. Phase and Frequency Correct PWM Mode
- •17.13. Timer/Counter Timing Diagrams
- •17.14. Register Description
- •17.14.1. Timer/Counter0 Control Register A
- •17.14.2. Timer/Counter0 Control Register B
- •17.14.3. Timer/Counter0 Control Register C
- •17.14.4. Timer/Counter 0 Low and High byte
- •17.14.5. Output Comparte Register A 0 Low and High byte
- •17.14.6. Output Comparte Register B 0 Low and High byte
- •17.14.7. Input Capture Register 0 Low and High byte
- •17.14.8. Timer/Counter0 Interrupt Mask Register
- •17.14.9. Timer/Counter0 Interrupt Flag Register
- •17.14.10. General Timer/Counter Control Register
- •18. AC - Analog Comparator
- •18.1. Overview
- •18.2. Features
- •18.3. Block Diagram
- •18.4. Register Description
- •18.4.1. Analog Comparator Control and Status Register
- •18.4.2. Analog Comparator Control and Status Register 0
- •18.4.3. Digital Input Disable Register 0
- •19. ADC - Analog to Digital Converter
- •19.1. Overview
- •19.2. Features
- •19.3. Block Diagram
- •19.4. Operation
- •19.5. Starting a Conversion
- •19.6. Prescaling and Conversion Timing
- •19.7. Changing Channel or Reference Selection
- •19.8. ADC Input Channels
- •19.9. ADC Voltage Reference
- •19.10. ADC Noise Canceler
- •19.11. Analog Input Circuitry
- •19.12. Analog Noise Canceling Techniques
- •19.13. ADC Accuracy Definitions
- •19.14. ADC Conversion Result
- •19.15. Register Description
- •19.15.1. ADC Multiplexer Selection Register
- •19.15.2. ADC Control and Status Register A
- •19.15.3. ADC Control and Status Register B
- •19.15.4. ADC Data Register Low and High Byte (ADLAR=0)
- •19.15.5. ADC Data Register Low and High Byte (ADLAR=1)
- •19.15.6. Digital Input Disable Register 0
- •20.1. Overview
- •20.2. Features
- •20.3.2. Flash Memory
- •20.3.3. Configuration Section
- •20.3.3.1. Latching of Configuration Bits
- •20.3.4. Signature Section
- •20.3.4.1. Signature Row Summary
- •20.3.4.1.1. Device ID n
- •20.3.4.1.2. Serial Number Byte n
- •20.3.5. Calibration Section
- •20.4. Accessing the NVM
- •20.4.1. Addressing the Flash
- •20.4.2. Reading the Flash
- •20.4.3. Programming the Flash
- •20.4.3.1. Chip Erase
- •20.4.3.2. Erasing the Code Section
- •20.4.3.3. Writing a Code Word
- •20.4.3.4. Erasing the Configuration Section
- •20.4.3.5. Writing a Configuration Word
- •20.4.4. Reading NVM Lock Bits
- •20.4.5. Writing NVM Lock Bits
- •20.5. Self programming
- •20.6. External Programming
- •20.6.1. Entering External Programming Mode
- •20.6.2. Exiting External Programming Mode
- •20.7. Register Description
- •21.1. Overview
- •21.2. Features
- •21.3. Block Diagram
- •21.4. Physical Layer of Tiny Programming Interface
- •21.4.1. Enabling
- •21.4.2. Disabling
- •21.4.3. Frame Format
- •21.4.4. Parity Bit Calculation
- •21.4.5. Supported Characters
- •21.4.6. Operation
- •21.4.7. Serial Data Reception
- •21.4.8. Serial Data Transmission
- •21.4.9. Collision Detection Exception
- •21.4.10. Direction Change
- •21.4.11. Access Layer of Tiny Programming Interface
- •21.4.11.1. Message format
- •21.4.11.2. Exception Handling and Synchronisation
- •21.5. Instruction Set
- •21.5.1. SLD - Serial LoaD from data space using indirect addressing
- •21.5.2. SST - Serial STore to data space using indirect addressing
- •21.5.3. SSTPR - Serial STore to Pointer Register
- •21.5.4. SIN - Serial IN from i/o space using direct addressing
- •21.5.5. SOUT - Serial OUT to i/o space using direct addressing
- •21.5.6. SLDCS - Serial LoaD data from Control and Status space using direct addressing
- •21.5.7. SSTCS - Serial STore data to Control and Status space using direct addressing
- •21.5.8. SKEY - Serial KEY signaling
- •21.7. Control and Status Space Register Descriptions
- •21.7.1. Tiny Programming Interface Identification Register
- •21.7.2. Tiny Programming Interface Physical Layer Control Register
- •21.7.3. Tiny Programming Interface Status Register
- •22. Electrical Characteristics
- •22.1. Absolute Maximum Ratings*
- •22.2. DC Characteristics
- •22.3. Speed
- •22.4. Clock Characteristics
- •22.4.1. Accuracy of Calibrated Internal Oscillator
- •22.4.2. External Clock Drive
- •22.5. System and Reset Characteristics
- •22.6. Analog Comparator Characteristics
- •22.7. ADC Characteristics
- •22.8. Serial Programming Characteristics
- •23. Typical Characteristics
- •23.1. Active Supply Current
- •23.2. Idle Supply Current
- •23.3. Supply Current of I/O Modules
- •23.5. Pin Driver Strength
- •23.6. Pin Threshold and Hysteresis
- •23.7. Analog Comparator Offset
- •23.9. Internal Oscillator Speed
- •23.10. VLM Thresholds
- •23.11. Current Consumption of Peripheral Units
- •23.12. Current Consumption in Reset and Reset Pulsewidth
- •24. Register Summary
- •24.1. Note
- •25. Instruction Set Summary
- •26. Packaging Information
- •27. Errata
- •27.1. ATtiny102
- •27.2. ATtiny104
- •28. Datasheet Revision History
3.The Power-on Reset will not work unless the supply voltage has been below VPOT(falling)
22.5.2.VCC Level Monitor
Table 22-6. Voltage Level Monitor Thresholds
Parameter |
Min |
Typ (1) |
Max |
Units |
Trigger level VLM1L |
1.1 |
1.4 |
1.6 |
V |
|
|
|
|
|
Trigger level VLM1H |
1.4 |
1.6 |
1.8 |
|
|
|
|
|
|
Trigger level VLM2 |
2.0 |
2.5 |
2.7 |
|
|
|
|
|
|
Trigger level VLM3 |
3.2 |
3.7 |
4.5 |
|
|
|
|
|
|
Settling time VMLM2,VLM3 (VLM1H,VLM1L) |
|
5 (50) |
|
µs |
|
|
|
|
|
Note:
1.Typical values at room temperature
22.6.Analog Comparator Characteristics
Table 22-7. Analog Comparator Characteristics, TA = -40°C to 125°C
Symbol |
Parameter |
Condition |
Min |
Typ |
Max |
Units |
|
|
|
|
|
|
|
VAIO |
Input Offset Voltage |
VCC = 5V, VIN = VCC / 2 |
|
10 |
40 |
mV |
ILAC |
Input Leakage Current |
VCC = 5V, VIN = VCC / 2 |
-50 |
|
50 |
nA |
tAPD* |
Analog Propagation Delay |
VCC = 2.7V |
|
150 |
|
ns |
|
(from saturation to 100mV overdrive) |
|
|
|
|
|
|
VCC = 4.0V |
|
185 |
|
|
|
|
|
|
|
|
||
|
Analog Propagation Delay |
VCC = 2.7V |
|
135 |
|
|
|
(from step change of 100mV) |
|
|
|
|
|
|
VCC = 4.0V |
|
160 |
|
|
|
|
|
|
|
|
||
tDPD |
Digital Propagation Delay |
VCC = 1.8V - 5.5V |
|
1 |
2 |
CLK |
Note: *: 15ns delay IP to pad removed
Atmel ATtiny102 / ATtiny104 [DATASHEET] 215
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
22.7.ADC Characteristics
Table 22-8. ADC Characteristics. T = -40°C to 125°C VCC = 1.8V - 5.5V
Symbol |
Parameter |
Condition |
Min |
Typ |
Max |
Units |
|
|
Resolution |
|
|
|
10 |
Bits |
|
|
|
|
|
|
|
|
|
|
Absolute accuracy |
VREF = VCC = 4.3V, |
|
2 |
|
LSB |
|
|
(Including INL, DNL, and |
ADC clock = 200 kHz |
|
|
|
|
|
|
Quantization, Gain and |
|
|
|
|
|
|
|
VREF = VCC = 4.3V, |
|
3 |
|
|
||
|
Offset Errors) |
|
|
|
|||
|
ADC clock = 1 MHz |
|
|
|
|
||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
VREF = VCC = 4.3V, ADC clock = 200 |
|
1.5 |
|
LSB |
|
|
|
kHz |
|
|
|
|
|
|
|
Noise Reduction Mode |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VREF = VCC = 4.3V, ADC clock = 1 |
|
2.5 |
|
|
|
|
|
MHz |
|
|
|
|
|
|
|
Noise Reduction Mode |
|
|
|
|
|
|
|
|
|
|
|
|
|
INL |
Integral Non-Linearity |
VREF = VCC = 4.0V, |
0.51 |
0.68 |
0.88 |
LSB |
|
|
(Accuracy after Offset and |
ADC clock = 200 kHz |
|
|
|
|
|
|
Gain Calibration) |
|
|
|
|
|
|
|
VREF = VCC = 4.0V, |
0.39 |
0.62 |
0.92 |
|
||
|
|
|
|||||
|
|
ADC clock = 1 MHz |
|
|
|
|
|
|
|
|
|
|
|
|
|
DNL |
Differential Non-linearity |
VREF = VCC = 4.0V, ADC clock = 200 |
0.42 |
0.49 |
0.73 |
LSB |
|
|
|
kHz |
|
|
|
|
|
|
|
VREF = VCC = 4.0V, |
0.22 |
0.48 |
0.55 |
|
|
|
|
ADC clock = 1 MHz |
|
|
|
|
|
|
Gain Error |
VREF = VCC = 4.0V, ADC clock = 200 |
-7.2 |
-4 |
-1 |
LSB |
|
|
|
kHz |
|
|
|
|
|
|
|
Int VREF = 1.1V, VCC = 4.0V, ADC clock |
-41.3 |
-13.3 |
-1.9 |
|
|
|
|
= 200 kHz |
|
|
|
|
|
|
|
Int VREF = 2.2V, VCC = 4.0V, ADC clock |
-38.3 |
-8.7 |
3.1 |
|
|
|
|
= 200 kHz |
|
|
|
|
|
|
|
Int VREF = 4.3V, VCC = 4.0V, ADC clock |
-80.4 |
-3.2 |
9.9 |
|
|
|
|
= 200 kHz |
|
|
|
|
|
|
Offset Error |
VREF = VCC = 4.0V, ADC clock = 200 |
3.0 |
5.1 |
8 |
LSB |
|
|
|
kHz |
|
|
|
|
|
|
|
Int VREF = 1.1V, VCC = 4.0V, ADC clock |
-54 |
9.1 |
2 |
|
|
|
|
= 200 kHz |
|
|
|
|
|
|
|
Int VREF = 2.2V, VCC = 4.0V, ADC clock |
2 |
5.4 |
11 |
|
|
|
|
= 200 kHz |
|
|
|
|
|
|
|
Int VREF = 4.3V, VCC = 4.0V, ADC clock |
1 |
3.4 |
5.4 |
|
|
|
|
= 200 kHz |
|
|
|
|
|
|
|
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
216 |
||||
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Symbol |
Parameter |
Condition |
Min |
Typ |
Max |
Units |
|
|
|
Conversion Time |
Single Conversion |
13 |
|
260 |
µs |
|
|
|
|
|
|
|
|
|
|
|
|
Clock Frequency |
|
50 |
|
1000 |
kHz |
|
|
|
|
|
|
|
|
|
|
|
VIN |
Input Voltage |
|
GND |
|
VREF |
V |
|
|
|
Input Bandwidth |
|
|
38.5 |
|
kHz |
|
|
|
|
|
|
|
|
|
|
|
RAIN |
Analog Input Resistance |
|
|
100 |
|
MΩ |
|
|
|
ADC Conversion Output |
|
0 |
|
1023 |
LSB |
|
|
|
|
|
|
|
|
|
|
22.8.Serial Programming Characteristics
Figure 22-3. Serial Programming Timing
Re ce ive Mode |
|
Tra ns mit Mode |
TP IDATA
tIVCH |
|
tCHIX |
|
tCLOV |
TP ICLK
tCLCH tCHCL
tCLCL
Table 22-9. Serial Programming Characteristics, TA = -40°C to 125°C, VCC = 5V ± 5% (Unless Otherwise
Noted)
Symbol |
Parameter |
Min |
Typ |
Max |
Units |
|
1/tCLCL |
Clock Frequency |
|
|
2 |
MHz |
|
tCLCL |
Clock Period |
500 |
|
|
ns |
|
tCLCH |
Clock Low Pulse Width |
200 |
|
|
ns |
|
tCHCH |
Clock High Pulse Width |
200 |
|
|
ns |
|
tIVCH |
Data Input to Clock High Setup Time |
50 |
|
|
ns |
|
tCHIX |
Data Input Hold Time After Clock High |
100 |
|
|
ns |
|
tCLOV |
Data Output Valid After Clock Low Time |
|
|
200 |
ns |
Atmel ATtiny102 / ATtiny104 [DATASHEET] 217
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016