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Write messages. A write message is a request to write data. The write message is sent entirely by the external programmer. This message type is used with the SSTCS, SST, STPR, SOUT and SKEY instructions.

Read messages. A read message is a request to read data. The TPI reacts to the request by sending the byte operands. This message type is used with the SLDCS, SLD and SIN instructions.

All the instructions except the SKEY instruction require the instruction to be followed by one byte operand. The SKEY instruction requires 8 byte operands. For more information, see the TPI instruction set.

21.4.11.2. Exception Handling and Synchronisation

Several situations are considered exceptions from normal operation of the TPI. When the TPI physical layer is in receive mode, these exceptions are:

The TPI physical layer detects a parity error.

The TPI physical layer detects a frame error.

The TPI physical layer recognizes a BREAK character.

When the TPI physical layer is in transmit mode, the possible exceptions are:

The TPI physical layer detects a data collision.

All these exceptions are signalized to the TPI access layer. The access layer responds to an exception by aborting any on-going operation and enters the error state. The access layer will stay in the error state until a BREAK character has been received, after which it is taken back to its default state. As a consequence, the external programmer can always synchronize the protocol by simply transmitting two successive BREAK characters.

21.5.Instruction Set

The TPI has a compact instruction set that is used to access the TPI Control and Status Space (CSS) and the data space. The instructions allow the external programmer to access the TPI, the NVM Controller and the NVM memories. All instructions except SKEY require one byte operand following the instruction. The SKEY instruction is followed by 8 data bytes. All instructions are byte-sized.

Table 21-1. Instruction Set Summary

Mnemonic

Operand

Description

Operation

 

 

 

 

SLD

data, PR

Serial LoaD from data space using indirect addressing

data ← DS[PR]

 

 

 

 

SLD

data, PR+

Serial LoaD from data space using indirect addressing and

data ← DS[PR]

 

 

post-increment

PR ← PR+1

 

 

 

 

 

 

 

SST

PR, data

Serial STore to data space using indirect addressing

DS[PR] ← data

 

 

 

 

SST

PR+, data

Serial STore to data space using indirect addressing and

DS[PR] ← data

 

 

post-increment

 

 

PR ← PR+1

 

 

 

 

 

 

 

SSTPR

PR, a

Serial STore to Pointer Register using direct addressing

PR[a] ← data

 

 

 

 

SIN

data, a

Serial IN from data space

data ← I/O[a]

 

 

 

 

SOUT

a, data

Serial OUT to data space

I/O[a] ← data

 

 

 

 

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Mnemonic

Operand

Description

Operation

 

 

 

 

 

 

 

 

SLDCS

data, a

Serial LoaD from Control and Status space using direct

data ← CSS[a]

 

 

 

 

addressing

 

 

 

 

 

 

 

 

 

SSTCS

a, data

Serial STore to Control and Status space using direct

CSS[a] ← data

 

 

 

 

addressing

 

 

 

 

 

 

 

 

 

SKEY

Key, {8{data}}

Serial KEY

Key ← {8{data}}

 

 

 

 

 

 

 

21.5.1. SLD - Serial LoaD from data space using indirect addressing

The SLD instruction uses indirect addressing to load data from the data space to the TPI physical layer shift-register for serial read-out. The data space location is pointed by the Pointer Register (PR), where the address must have been stored before data is accessed. The Pointer Register is either left unchanged by the operation, or post-incremented.

Table 21-2. The Serial Load from Data Space (SLD) Instruction

Operation

Opcode

Remarks

Register

 

 

 

 

data ← DS[PR]

0010 0000

PR ← PR

Unchanged

 

 

 

 

data ← DS[PR]

0010 0100

PR ← PR + 1

Post increment

 

 

 

 

21.5.2. SST - Serial STore to data space using indirect addressing

The SST instruction uses indirect addressing to store into data space the byte that is shifted into the physical layer shift register. The data space location is pointed by the Pointer Register (PR), where the address must have been stored before the operation. The Pointer Register can be either left unchanged by the operation, or it can be post-incremented.

Table 21-3. The Serial Store to Data Space (SST) Instruction

Operation

Opcode

Remarks

Register

 

 

 

 

DS[PR] ← data

0110 0000

PR ← PR

Unchanged

 

 

 

 

DS[PR] ← data

0110 0000

PR ← PR + 1

Post increment

 

 

 

 

21.5.3. SSTPR - Serial STore to Pointer Register

The SSTPR instruction stores the data byte that is shifted into the physical layer shift register to the Pointer Register (PR). The address bit of the instruction specifies which byte of the Pointer Register is accessed.

Table 21-4. The Serial Store to Pointer Register (SSTPR) Instruction

Operation

Opcode

Remarks

 

 

 

PR[a] ← data

0110 100a

Bit ‘a’ addresses Pointer Register byte

 

 

 

21.5.4. SIN - Serial IN from i/o space using direct addressing

The SIN instruction loads data byte from the I/O space to the shift register of the physical layer for serial read-out. The instuction uses direct addressing, the address consisting of the 6 address bits of the instruction.

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Table 21-5. The Serial IN from i/o space (SIN) Instruction

Operation

Opcode

Remarks

 

 

 

data ← I/O[a]

0aa1 aaaa

Bits marked ‘a’ form the direct, 6-bit address

 

 

 

21.5.5. SOUT - Serial OUT to i/o space using direct addressing

The SOUT instruction stores the data byte that is shifted into the physical layer shift register to the I/O space. The instruction uses direct addressing, the address consisting of the 6 address bits of the instruction.

Table 21-6. The Serial OUT to i/o space (SOUT) Instruction

Operation

Opcode

Remarks

 

 

 

I/O[a] ← data

1aa1 aaaa

Bits marked ‘a’ form the direct, 6-bit address

 

 

 

21.5.6. SLDCS - Serial LoaD data from Control and Status space using direct addressing

The SLDCS instruction loads data byte from the TPI Control and Status Space to the TPI physical layer shift register for serial read-out. The SLDCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction.

Table 21-7. The Serial Load Data from Control and Status space (SLDCS) Instruction

Operation

Opcode

Remarks

 

 

 

data ← CSS[a]

1000 aaaa

Bits marked ‘a’ form the direct, 4-bit address

 

 

 

21.5.7. SSTCS - Serial STore data to Control and Status space using direct addressing

The SSTCS instruction stores the data byte that is shifted into the TPI physical layer shift register to the TPI Control and Status Space. The SSTCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction.

Table 21-8. The Serial STore data to Control and Status space (SSTCS) Instruction

Operation

Opcode

Remarks

 

 

 

CSS[a] ← data

1100 aaaa

Bits marked ‘a’ form the direct, 4-bit address

 

 

 

21.5.8. SKEY - Serial KEY signaling

The SKEY instruction is used to signal the activation key that enables NVM programming. The SKEY instruction is followed by the 8 data bytes that includes the activation key.

Table 21-9. The Serial KEY signaling (SKEY) Instruction

Operation

Opcode

Remarks

 

 

 

Key ← {8[data}}

1110 0000

Data bytes follow after instruction

 

 

 

21.6.Accessing the Non-Volatile Memory Controller

By default, NVM programming is not enabled. In order to access the NVM Controller and be able to program the non-volatile memories, a unique key must be sent using the SKEY instruction.

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