- •Introduction
- •Feature
- •Table of Contents
- •1. Description
- •2. Configuration Summary
- •3. Ordering Information
- •4. Block Diagram
- •5. Pin Configurations
- •5.1. Pin Descriptions
- •5.1.3. Port A (PA[7:0])
- •5.1.4. Port B (PB[3:0])
- •5.1.5. RESET
- •6. I/O Multiplexing
- •7. General Information
- •7.1. Resources
- •7.2. Data Retention
- •7.3. About Code Examples
- •8. AVR CPU Core
- •8.1. Overview
- •8.2. Features
- •8.3. Block Diagram
- •8.4. ALU – Arithmetic Logic Unit
- •8.5. Status Register
- •8.6. General Purpose Register File
- •8.8. Stack Pointer
- •8.10. Instruction Execution Timing
- •8.11. Reset and Interrupt Handling
- •8.11.1. Interrupt Response Time
- •8.12. Register Description
- •8.12.1. Configuration Change Protection Register
- •8.12.2. Stack Pointer Register Low and High byte
- •8.12.3. Status Register
- •9. AVR Memories
- •9.1. Overview
- •9.2. Features
- •9.4. SRAM Data Memory
- •9.4.1. Data Memory Access Times
- •9.5. I/O Memory
- •10. Clock System
- •10.1. Overview
- •10.2. Clock Distribution
- •10.3. Clock Subsystems
- •10.4. Clock Sources
- •10.4.1. Calibrated Internal 8MHz Oscillator
- •10.4.2. External Clock
- •10.4.3. Internal 128kHz Oscillator
- •10.4.4. Switching Clock Source
- •10.4.5. Default Clock Source
- •10.5. System Clock Prescaler
- •10.5.1. Switching Prescaler Setting
- •10.6. Starting
- •10.6.1. Starting from Reset
- •10.6.2. Starting from Power-Down Mode
- •10.6.3. Starting from Idle / ADC Noise Reduction / Standby Mode
- •10.7. Register Description
- •10.7.1. Clock Main Settings Register
- •10.7.2. Oscillator Calibration Register
- •10.7.3. Clock Prescaler Register
- •11. Power Management and Sleep Modes
- •11.1. Overview
- •11.2. Features
- •11.3. Sleep Modes
- •11.3.1. Idle Mode
- •11.3.2. ADC Noise Reduction Mode
- •11.3.4. Standby Mode
- •11.4. Power Reduction Register
- •11.5. Minimizing Power Consumption
- •11.5.1. Analog Comparator
- •11.5.2. Analog to Digital Converter
- •11.5.3. Internal Voltage Reference
- •11.5.4. Watchdog Timer
- •11.5.5. Port Pins
- •11.6. Register Description
- •11.6.1. Sleep Mode Control Register
- •11.6.2. Power Reduction Register
- •12. SCRST - System Control and Reset
- •12.1. Overview
- •12.2. Features
- •12.3. Resetting the AVR
- •12.4. Reset Sources
- •12.4.3. External Reset
- •12.4.4. Watchdog System Reset
- •12.5. Watchdog Timer
- •12.5.1. Overview
- •12.5.2. Procedure for Changing the Watchdog Timer Configuration
- •12.5.2.1. Safety Level 1
- •12.5.2.2. Safety Level 2
- •12.5.3. Code Examples
- •12.6. Register Description
- •12.6.1. Watchdog Timer Control Register
- •12.6.2. VCC Level Monitoring Control and Status register
- •12.6.3. Reset Flag Register
- •13. Interrupts
- •13.1. Overview
- •13.2. Interrupt Vectors
- •13.3. External Interrupts
- •13.3.1. Low Level Interrupt
- •13.3.2. Pin Change Interrupt Timing
- •13.4. Register Description
- •13.4.1. External Interrupt Control Register A
- •13.4.2. External Interrupt Mask Register
- •13.4.3. External Interrupt Flag Register
- •13.4.4. Pin Change Interrupt Control Register
- •13.4.5. Pin Change Interrupt Flag Register
- •13.4.6. Pin Change Mask Register 0
- •13.4.7. Pin Change Mask Register 1
- •14. I/O-Ports
- •14.1. Overview
- •14.2. Features
- •14.3. I/O Pin Equivalent Schematic
- •14.4. Ports as General Digital I/O
- •14.4.1. Configuring the Pin
- •14.4.2. Toggling the Pin
- •14.4.4. Reading the Pin Value
- •14.4.5. Digital Input Enable and Sleep Modes
- •14.4.6. Unconnected Pins
- •14.4.7. Program Example
- •14.4.8. Alternate Port Functions
- •14.4.8.1. Alternate Functions of Port A
- •14.4.8.2. Alternate Functions of Port B
- •14.5. Register Description
- •14.5.1. Port A Input Pins Address
- •14.5.2. Port A Data Direction Register
- •14.5.3. Port A Data Register
- •14.5.5. Port B Input Pins Address
- •14.5.6. Port B Data Direction Register
- •14.5.7. Port B Data Register
- •14.5.9. Port Control Register
- •15. USART - Universal Synchronous Asynchronous Receiver Transceiver
- •15.1. Overview
- •15.2. Features
- •15.3. Block Diagram
- •15.4. Clock Generation
- •15.4.1. Internal Clock Generation – The Baud Rate Generator
- •15.4.2. Double Speed Operation (U2X0)
- •15.4.3. External Clock
- •15.4.4. Synchronous Clock Operation
- •15.5. Frame Formats
- •15.5.1. Parity Bit Calculation
- •15.6. USART Initialization
- •15.7. Data Transmission – The USART Transmitter
- •15.7.1. Sending Frames with 5 to 8 Data Bits
- •15.7.2. Sending Frames with 9 Data Bit
- •15.7.3. Transmitter Flags and Interrupts
- •15.7.4. Parity Generator
- •15.7.5. Disabling the Transmitter
- •15.8. Data Reception – The USART Receiver
- •15.8.1. Receiving Frames with 5 to 8 Data Bits
- •15.8.2. Receiving Frames with 9 Data Bits
- •15.8.3. Receive Compete Flag and Interrupt
- •15.8.4. Receiver Error Flags
- •15.8.5. Parity Checker
- •15.8.6. Disabling the Receiver
- •15.8.7. Flushing the Receive Buffer
- •15.9. Asynchronous Data Reception
- •15.9.1. Asynchronous Clock Recovery
- •15.9.2. Asynchronous Data Recovery
- •15.9.3. Asynchronous Operational Range
- •15.9.4. Start Frame Detection
- •15.10. Multi-Processor Communication Mode
- •15.10.1. Using MPCMn
- •15.11. Examples of Baud Rate Setting
- •15.12. Register Description
- •15.12.1. USART I/O Data Register 0
- •15.12.2. USART Control and Status Register 0 A
- •15.12.3. USART Control and Status Register 0 B
- •15.12.4. USART Control and Status Register 0 C
- •15.12.5. USART Control and Status Register 0 D
- •15.12.6. USART Baud Rate 0 Register Low and High byte
- •16. USARTSPI - USART in SPI Mode
- •16.1. Overview
- •16.2. Features
- •16.3. Clock Generation
- •16.4. SPI Data Modes and Timing
- •16.5. Frame Formats
- •16.5.1. USART MSPIM Initialization
- •16.6. Data Transfer
- •16.6.1. Transmitter and Receiver Flags and Interrupts
- •16.6.2. Disabling the Transmitter or Receiver
- •16.7. AVR USART MSPIM vs. AVR SPI
- •16.8. Register Description
- •17.1. Overview
- •17.2. Features
- •17.3. Block Diagram
- •17.4. Definitions
- •17.5. Registers
- •17.6.1. Reusing the Temporary High Byte Register
- •17.7. Timer/Counter Clock Sources
- •17.7.1. Internal Clock Source - Prescaler
- •17.7.2. Prescaler Reset
- •17.7.3. External Clock Source
- •17.8. Counter Unit
- •17.9. Input Capture Unit
- •17.9.1. Input Capture Trigger Source
- •17.9.2. Noise Canceler
- •17.9.3. Using the Input Capture Unit
- •17.10. Output Compare Units
- •17.10.1. Force Output Compare
- •17.10.2. Compare Match Blocking by TCNT0 Write
- •17.10.3. Using the Output Compare Unit
- •17.11. Compare Match Output Unit
- •17.11.1. Compare Output Mode and Waveform Generation
- •17.12. Modes of Operation
- •17.12.1. Normal Mode
- •17.12.2. Clear Timer on Compare Match (CTC) Mode
- •17.12.3. Fast PWM Mode
- •17.12.4. Phase Correct PWM Mode
- •17.12.5. Phase and Frequency Correct PWM Mode
- •17.13. Timer/Counter Timing Diagrams
- •17.14. Register Description
- •17.14.1. Timer/Counter0 Control Register A
- •17.14.2. Timer/Counter0 Control Register B
- •17.14.3. Timer/Counter0 Control Register C
- •17.14.4. Timer/Counter 0 Low and High byte
- •17.14.5. Output Comparte Register A 0 Low and High byte
- •17.14.6. Output Comparte Register B 0 Low and High byte
- •17.14.7. Input Capture Register 0 Low and High byte
- •17.14.8. Timer/Counter0 Interrupt Mask Register
- •17.14.9. Timer/Counter0 Interrupt Flag Register
- •17.14.10. General Timer/Counter Control Register
- •18. AC - Analog Comparator
- •18.1. Overview
- •18.2. Features
- •18.3. Block Diagram
- •18.4. Register Description
- •18.4.1. Analog Comparator Control and Status Register
- •18.4.2. Analog Comparator Control and Status Register 0
- •18.4.3. Digital Input Disable Register 0
- •19. ADC - Analog to Digital Converter
- •19.1. Overview
- •19.2. Features
- •19.3. Block Diagram
- •19.4. Operation
- •19.5. Starting a Conversion
- •19.6. Prescaling and Conversion Timing
- •19.7. Changing Channel or Reference Selection
- •19.8. ADC Input Channels
- •19.9. ADC Voltage Reference
- •19.10. ADC Noise Canceler
- •19.11. Analog Input Circuitry
- •19.12. Analog Noise Canceling Techniques
- •19.13. ADC Accuracy Definitions
- •19.14. ADC Conversion Result
- •19.15. Register Description
- •19.15.1. ADC Multiplexer Selection Register
- •19.15.2. ADC Control and Status Register A
- •19.15.3. ADC Control and Status Register B
- •19.15.4. ADC Data Register Low and High Byte (ADLAR=0)
- •19.15.5. ADC Data Register Low and High Byte (ADLAR=1)
- •19.15.6. Digital Input Disable Register 0
- •20.1. Overview
- •20.2. Features
- •20.3.2. Flash Memory
- •20.3.3. Configuration Section
- •20.3.3.1. Latching of Configuration Bits
- •20.3.4. Signature Section
- •20.3.4.1. Signature Row Summary
- •20.3.4.1.1. Device ID n
- •20.3.4.1.2. Serial Number Byte n
- •20.3.5. Calibration Section
- •20.4. Accessing the NVM
- •20.4.1. Addressing the Flash
- •20.4.2. Reading the Flash
- •20.4.3. Programming the Flash
- •20.4.3.1. Chip Erase
- •20.4.3.2. Erasing the Code Section
- •20.4.3.3. Writing a Code Word
- •20.4.3.4. Erasing the Configuration Section
- •20.4.3.5. Writing a Configuration Word
- •20.4.4. Reading NVM Lock Bits
- •20.4.5. Writing NVM Lock Bits
- •20.5. Self programming
- •20.6. External Programming
- •20.6.1. Entering External Programming Mode
- •20.6.2. Exiting External Programming Mode
- •20.7. Register Description
- •21.1. Overview
- •21.2. Features
- •21.3. Block Diagram
- •21.4. Physical Layer of Tiny Programming Interface
- •21.4.1. Enabling
- •21.4.2. Disabling
- •21.4.3. Frame Format
- •21.4.4. Parity Bit Calculation
- •21.4.5. Supported Characters
- •21.4.6. Operation
- •21.4.7. Serial Data Reception
- •21.4.8. Serial Data Transmission
- •21.4.9. Collision Detection Exception
- •21.4.10. Direction Change
- •21.4.11. Access Layer of Tiny Programming Interface
- •21.4.11.1. Message format
- •21.4.11.2. Exception Handling and Synchronisation
- •21.5. Instruction Set
- •21.5.1. SLD - Serial LoaD from data space using indirect addressing
- •21.5.2. SST - Serial STore to data space using indirect addressing
- •21.5.3. SSTPR - Serial STore to Pointer Register
- •21.5.4. SIN - Serial IN from i/o space using direct addressing
- •21.5.5. SOUT - Serial OUT to i/o space using direct addressing
- •21.5.6. SLDCS - Serial LoaD data from Control and Status space using direct addressing
- •21.5.7. SSTCS - Serial STore data to Control and Status space using direct addressing
- •21.5.8. SKEY - Serial KEY signaling
- •21.7. Control and Status Space Register Descriptions
- •21.7.1. Tiny Programming Interface Identification Register
- •21.7.2. Tiny Programming Interface Physical Layer Control Register
- •21.7.3. Tiny Programming Interface Status Register
- •22. Electrical Characteristics
- •22.1. Absolute Maximum Ratings*
- •22.2. DC Characteristics
- •22.3. Speed
- •22.4. Clock Characteristics
- •22.4.1. Accuracy of Calibrated Internal Oscillator
- •22.4.2. External Clock Drive
- •22.5. System and Reset Characteristics
- •22.6. Analog Comparator Characteristics
- •22.7. ADC Characteristics
- •22.8. Serial Programming Characteristics
- •23. Typical Characteristics
- •23.1. Active Supply Current
- •23.2. Idle Supply Current
- •23.3. Supply Current of I/O Modules
- •23.5. Pin Driver Strength
- •23.6. Pin Threshold and Hysteresis
- •23.7. Analog Comparator Offset
- •23.9. Internal Oscillator Speed
- •23.10. VLM Thresholds
- •23.11. Current Consumption of Peripheral Units
- •23.12. Current Consumption in Reset and Reset Pulsewidth
- •24. Register Summary
- •24.1. Note
- •25. Instruction Set Summary
- •26. Packaging Information
- •27. Errata
- •27.1. ATtiny102
- •27.2. ATtiny104
- •28. Datasheet Revision History
•Write messages. A write message is a request to write data. The write message is sent entirely by the external programmer. This message type is used with the SSTCS, SST, STPR, SOUT and SKEY instructions.
•Read messages. A read message is a request to read data. The TPI reacts to the request by sending the byte operands. This message type is used with the SLDCS, SLD and SIN instructions.
All the instructions except the SKEY instruction require the instruction to be followed by one byte operand. The SKEY instruction requires 8 byte operands. For more information, see the TPI instruction set.
21.4.11.2. Exception Handling and Synchronisation
Several situations are considered exceptions from normal operation of the TPI. When the TPI physical layer is in receive mode, these exceptions are:
•The TPI physical layer detects a parity error.
•The TPI physical layer detects a frame error.
•The TPI physical layer recognizes a BREAK character.
When the TPI physical layer is in transmit mode, the possible exceptions are:
•The TPI physical layer detects a data collision.
All these exceptions are signalized to the TPI access layer. The access layer responds to an exception by aborting any on-going operation and enters the error state. The access layer will stay in the error state until a BREAK character has been received, after which it is taken back to its default state. As a consequence, the external programmer can always synchronize the protocol by simply transmitting two successive BREAK characters.
21.5.Instruction Set
The TPI has a compact instruction set that is used to access the TPI Control and Status Space (CSS) and the data space. The instructions allow the external programmer to access the TPI, the NVM Controller and the NVM memories. All instructions except SKEY require one byte operand following the instruction. The SKEY instruction is followed by 8 data bytes. All instructions are byte-sized.
Table 21-1. Instruction Set Summary
Mnemonic |
Operand |
Description |
Operation |
|
|
|
|
SLD |
data, PR |
Serial LoaD from data space using indirect addressing |
data ← DS[PR] |
|
|
|
|
SLD |
data, PR+ |
Serial LoaD from data space using indirect addressing and |
data ← DS[PR] |
|
|
post-increment |
PR ← PR+1 |
|
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|
|
SST |
PR, data |
Serial STore to data space using indirect addressing |
DS[PR] ← data |
|
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|
SST |
PR+, data |
Serial STore to data space using indirect addressing and |
DS[PR] ← data |
|
|
post-increment |
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|
|
PR ← PR+1 |
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|
SSTPR |
PR, a |
Serial STore to Pointer Register using direct addressing |
PR[a] ← data |
|
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|
|
SIN |
data, a |
Serial IN from data space |
data ← I/O[a] |
|
|
|
|
SOUT |
a, data |
Serial OUT to data space |
I/O[a] ← data |
|
|
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|
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Mnemonic |
Operand |
Description |
Operation |
|
|
|
|
|
|
|
|
SLDCS |
data, a |
Serial LoaD from Control and Status space using direct |
data ← CSS[a] |
|
|
|
|
addressing |
|
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|
SSTCS |
a, data |
Serial STore to Control and Status space using direct |
CSS[a] ← data |
|
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addressing |
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SKEY |
Key, {8{data}} |
Serial KEY |
Key ← {8{data}} |
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21.5.1. SLD - Serial LoaD from data space using indirect addressing
The SLD instruction uses indirect addressing to load data from the data space to the TPI physical layer shift-register for serial read-out. The data space location is pointed by the Pointer Register (PR), where the address must have been stored before data is accessed. The Pointer Register is either left unchanged by the operation, or post-incremented.
Table 21-2. The Serial Load from Data Space (SLD) Instruction
Operation |
Opcode |
Remarks |
Register |
|
|
|
|
data ← DS[PR] |
0010 0000 |
PR ← PR |
Unchanged |
|
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|
|
data ← DS[PR] |
0010 0100 |
PR ← PR + 1 |
Post increment |
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21.5.2. SST - Serial STore to data space using indirect addressing
The SST instruction uses indirect addressing to store into data space the byte that is shifted into the physical layer shift register. The data space location is pointed by the Pointer Register (PR), where the address must have been stored before the operation. The Pointer Register can be either left unchanged by the operation, or it can be post-incremented.
Table 21-3. The Serial Store to Data Space (SST) Instruction
Operation |
Opcode |
Remarks |
Register |
|
|
|
|
DS[PR] ← data |
0110 0000 |
PR ← PR |
Unchanged |
|
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|
|
DS[PR] ← data |
0110 0000 |
PR ← PR + 1 |
Post increment |
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21.5.3. SSTPR - Serial STore to Pointer Register
The SSTPR instruction stores the data byte that is shifted into the physical layer shift register to the Pointer Register (PR). The address bit of the instruction specifies which byte of the Pointer Register is accessed.
Table 21-4. The Serial Store to Pointer Register (SSTPR) Instruction
Operation |
Opcode |
Remarks |
|
|
|
PR[a] ← data |
0110 100a |
Bit ‘a’ addresses Pointer Register byte |
|
|
|
21.5.4. SIN - Serial IN from i/o space using direct addressing
The SIN instruction loads data byte from the I/O space to the shift register of the physical layer for serial read-out. The instuction uses direct addressing, the address consisting of the 6 address bits of the instruction.
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Table 21-5. The Serial IN from i/o space (SIN) Instruction
Operation |
Opcode |
Remarks |
|
|
|
data ← I/O[a] |
0aa1 aaaa |
Bits marked ‘a’ form the direct, 6-bit address |
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|
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21.5.5. SOUT - Serial OUT to i/o space using direct addressing
The SOUT instruction stores the data byte that is shifted into the physical layer shift register to the I/O space. The instruction uses direct addressing, the address consisting of the 6 address bits of the instruction.
Table 21-6. The Serial OUT to i/o space (SOUT) Instruction
Operation |
Opcode |
Remarks |
|
|
|
I/O[a] ← data |
1aa1 aaaa |
Bits marked ‘a’ form the direct, 6-bit address |
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21.5.6. SLDCS - Serial LoaD data from Control and Status space using direct addressing
The SLDCS instruction loads data byte from the TPI Control and Status Space to the TPI physical layer shift register for serial read-out. The SLDCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction.
Table 21-7. The Serial Load Data from Control and Status space (SLDCS) Instruction
Operation |
Opcode |
Remarks |
|
|
|
data ← CSS[a] |
1000 aaaa |
Bits marked ‘a’ form the direct, 4-bit address |
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21.5.7. SSTCS - Serial STore data to Control and Status space using direct addressing
The SSTCS instruction stores the data byte that is shifted into the TPI physical layer shift register to the TPI Control and Status Space. The SSTCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction.
Table 21-8. The Serial STore data to Control and Status space (SSTCS) Instruction
Operation |
Opcode |
Remarks |
|
|
|
CSS[a] ← data |
1100 aaaa |
Bits marked ‘a’ form the direct, 4-bit address |
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21.5.8. SKEY - Serial KEY signaling
The SKEY instruction is used to signal the activation key that enables NVM programming. The SKEY instruction is followed by the 8 data bytes that includes the activation key.
Table 21-9. The Serial KEY signaling (SKEY) Instruction
Operation |
Opcode |
Remarks |
|
|
|
Key ← {8[data}} |
1110 0000 |
Data bytes follow after instruction |
|
|
|
21.6.Accessing the Non-Volatile Memory Controller
By default, NVM programming is not enabled. In order to access the NVM Controller and be able to program the non-volatile memories, a unique key must be sent using the SKEY instruction.
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