19.15.6.Digital Input Disable Register 0

When the respective bits are written to logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[7:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.

Name:  DIDR0 Offset:  0x17 Reset:  0x00 Property: -

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ADC0D, ADC1D, ADC2D, ADC3D, ADC4D, ADC5D, ADC6D, ADC7D: ADC Digital Input Disable

•ADC:

–When ADC0D or ADC1D is set to '1', the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[7:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.

•AC:

–When ADC0D or ADC1D is set to '1', the digital input buffer on pin AIN1 (ADC1) / AIN0 (ADC0) is disabled and the corresponding PIN register bit will read as zero. When used as an analog input but not required as a digital input the power consumption in the digital input buffer can be reduced by writing this bit to logic one.

–DIDR0[7:2] : these bits are not applicable for AC.

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20.MEMPROGMemory Programming

20.1.Overview

The Non-Volatile Memory (NVM) Controller manages all access to the Non-Volatile Memories. The NVM Controller controls all NVM timing and access privileges, and holds the status of the NVM.

During normal execution the CPU will execute code from the code section of the Flash memory (program memory). When entering sleep and no programming operations are active, the Flash memory is disabled to minimize power consumption.

All NVM are mapped to the data memory. Application software can read the NVM from the mapped locations of data memory using load instruction with indirect addressing.

The NVM has only one read port and, therefore, the next instruction and the data can not be read simultaneously. When the application reads data from NVM locations mapped to the data space, the data is read first before the next instruction is fetched. The CPU execution is here delayed by one system clock cycle.

Internal programming (self-programming) operations to NVM have been disabled and the NVM therefore appears to the application software as read-only. Internal write or erase operations of the NVM will not be successful.

The method used by the external programmer for writing the Non-Volatile Memories is referred to as external programming. External programming can be done both in-system or in mass production. The external programmer can read and program the NVM via the Tiny Programming Interface (TPI).

In the external programming mode all NVM can be read and programmed, except the signature and the calibration sections which are read-only.

NVM can be programmed between 1.8-5.5V.

20.2.Features

•Two Embedded Non-Volatile Memories:

–Non-Volatile Memory Lock bits (NVM Lock bits)

–Flash Memory

•Four Separate Sections Inside Flash Memory:

–Code Section (Program Memory)

–Signature Section

–Configuration Section

–Calibration Section

•Read Access to All Non-Volatile Memories from Application Software

•Read and Write Access to Non-Volatile Memories from External programmer:

–Read Access to All Non-Volatile Memories

–Write Access to NVM Lock Bits, Flash Code Section and Flash Configuration Section

•External Programming:

–Support for In-System and Mass Production Programming

–Programming Through the Tiny Programming Interface (TPI)

•High Security with NVM Lock Bits

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•Self-Programming Flash on Full Operating Voltage Range (1.8 – 5.5V)

20.3.Non-Volatile Memories (NVM)

The device has the following, embedded NVM:

•Non-Volatile Memory Lock Bits

•Flash memory with four separate sections

•1KB Flash Memory

–CPU execution will be halted while doing external programming

•Extra rows

–Flash - Unique ID needs to be added

20.3.1.Non-Volatile Memory Lock Bits

The device provides two Lock Bits.

Table 20-1. Lock Bit Byte

The Lock Bits can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional security. Lock Bits can be erased to "1" with the Chip Erase command, only.

Table 20-2. Lock Bit Protection Modes

Note: 

1.Program the configuration section bits before programming NVLB1 and NVLB2.

2."1" means unprogrammed, "0" means programmed

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