17.14.9. Timer/Counter0 Interrupt Flag Register

Name:  TIFR0 Offset:  0x2A Reset:  0x00

Property:

Bit 5 – ICF0: Timer/Counter0, Input Capture Flag

This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register (ICR0) is set by the WGM0[3:0] to be used as the TOP value, the ICF0 Flag is set when the counter reaches the TOP value.

ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF0 can be cleared by writing a logic one to its bit location.

Bit 2 – OCF0B: Timer/Counter0, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output Compare Register B (OCR0B).

Note that a Forced Output Compare (FOC0B) strobe will not set the OCF0B Flag.

OCF0B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF0B can be cleared by writing a logic one to its bit location.

Bit 1 – OCF0A: Timer/Counter0, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output Compare Register A (OCR0A).

Note that a Forced Output Compare (FOC0A) strobe will not set the OCF0A Flag.

OCF0A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF0A can be cleared by writing a logic one to its bit location.

Bit 0 – TOV0: Timer/Counter0, Overflow Flag

The setting of this flag is dependent of the WGM0[3:0] bits setting. In Normal and CTC modes, the TOV0 Flag is set when the timer overflows. Refer to Table 17-6 for the TOV0 Flag behavior when using another WGM0[3:0] bit setting.

TOV0 is automatically cleared when the Timer/Counter0 Overflow Interrupt Vector is executed. Alternatively, TOV0 can be cleared by writing a logic one to its bit location.

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17.14.10. General Timer/Counter Control Register

Name:  GTCCR Offset:  0x2F Reset:  0x00 Property: -

Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to '1' activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to '0', the PSR bit is cleared by hardware, and the Timer/Counter start counting.

Bit 1 – REMAP

This bit controls how the TIMER pins are mapped to pins as shown in the table:

Bit 0 – PSR: Prescaler 0 Reset Timer/Counter 0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.

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