Note:  The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B).

The next figure shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR0x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV0 Flag at BOTTOM.

Figure 17-14. Timer/Counter Timing Diagram, no Prescaling.

Note:  The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B).

The next figure shows the same timing data, but with the prescaler enabled.

Figure 17-15. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

clk

I/O

clk

Tn

(clk /8)

I/O

TOVn(FPWM) and ICF n(if used as TOP)

Note:  The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B).

17.14. Register Description

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17.14.1. Timer/Counter0 Control Register A

Name:  TCCR0A Offset:  0x2E Reset:  0x00 Property: -

Bits 7:6 – COM0An: Compare Output Mode for Channel A [n = 1:0]

Bits 5:4 – COM0Bn: Compare Output Mode for Channel B [n = 1:0]

The COM0A[1:0] and COM0B[1:0] control the Output Compare pins (OC0A and OC0B respectively) behavior. If one or both of the COM0A[1:0] bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM0B[1:0] bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver.

When the OC0A or OC0B is connected to the pin, the function of the COM0x[1:0] bits is dependent of the WGM0[3:0] bits setting. The table below shows the COM0x[1:0] bit functionality when the WGM0[3:0] bits are set to a Normal or a CTC mode (non-PWM).

Table 17-3. Compare Output Mode, non-PWM

The table below shows the COM0x[1:0] bit functionality when the WGM0[3:0] bits are set to the fast PWM mode.

Table 17-4. Compare Output Mode, Fast PWM

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Note: 

1.A special case occurs when OCR0A/OCR0B equals TOP and COM0A1/COM0B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.

The table below shows the COM0x[1:0] bit functionality when the WGM0[3:0] bits are set to the phase correct or the phase and frequency correct, PWM mode.

Table 17-5. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM

Note: 

1.A special case occurs when OCR0A/OCR0B equals TOP and COM0A1/COM0B1 is set. Refer to Phase Correct PWM Mode for details.

Bits 1:0 – WGM0n: Waveform Generation Mode [n = 1:0]

Combined with the WGM0[3:2] bits found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See Modes of Operation).

Table 17-6. Waveform Generation Mode Bit Description

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