/* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn)) );

/* Get and return received data from buffer */ return UDRn;

}

16.6.1.Transmitter and Receiver Flags and Interrupts

The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero.

16.6.2.Disabling the Transmitter or Receiver

The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation.

16.7.AVR USART MSPIM vs. AVR SPI

The USART in MSPIM mode is fully compatible with the AVR SPI regarding:

•Master mode timing diagram

•The UCPOLn bit functionality is identical to the SPI CPOL bit

•The UCPHAn bit functionality is identical to the SPI CPHA bit

•The UDORDn bit functionality is identical to the SPI DORD bit

However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of the control register bits, and that only master operation is supported by the USART in MSPIM mode, the following features differ between the two modules:

•The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer

•The USART in MSPIM mode receiver includes an additional buffer level

•The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode

•The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting UBRRn accordingly

•Interrupt timing is not compatible

•Pin control differs due to the master only operation of the USART in MSPIM mode

A comparison of the USART in MSPIM mode and the SPI pins is shown in the table below.

Table 16-3. Comparison of USART in MSPIM mode and SPI pins

16.8.Register Description

Refer to the USART Register Description.

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17.TC0 - 16-bit Timer/Counter0 with PWM

17.1.Overview

The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement.

A block diagram of the 16-bit Timer/Counter is shown below. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in Register Description. For the actual placement of I/O pins, refer to the Pin Configurations description.

Related Links

Pin Configurations on page 12

17.2.Features

•True 16-bit Design (i.e., allows 16-bit PWM)

•Two independent Output Compare Units

•Double Buffered Output Compare Registers

•One Input Capture Unit

•Input Capture Noise Canceler

•Clear Timer on Compare Match (Auto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Variable PWM Period

•Frequency Generator

•External Event Counter

•Independent interrupt Sources (TOV, OCFA, OCFB, and ICF)

17.3.Block Diagram

The Power Reduction TC0 bit in the Power Reduction Register (PRR0.PRTIM0) must be written to zero to enable the TC0 module.

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See the related links for actual pin placement.

17.4.Definitions

Many register and bit references in this section are written in general form:

•n=0 represents the Timer/Counter number

•x=A,B represents the Output Compare Unit A or B

However, when using the register or bit definitions in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value.

The following definitions are used throughout the section:

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Table 17-1. Definitions

17.5.Registers

The Timer/Counter (TCNT0), Output Compare Registers (OCRA/B), and Input Capture Register (ICR0) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in section Accessing 16-bit Registers.

The Timer/Counter Control Registers (TCCR0A/B/C) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the block diagram) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).

The double buffered Output Compare Registers (OCR0A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0A/B). See Output Compare Units. The compare match event will also set the Compare Match Flag (OCF0A/B) which can be used to generate an Output Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP0) or on the Analog Comparator pins. The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR0A Register, the ICR0 Register, or by a set of fixed values. When using OCR0A as TOP value in a PWM mode, the OCR0A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR0 Register can be used as an alternative, freeing the OCR0A to be used as PWM output.

Related Links

ICR0L and ICR0H on page 156

OCR0AL and OCR0AH on page 154

OCR0BL and OCR0BH on page 155

TCNT0L and TCNT0H on page 153

TCCR0A on page 147

TCCR0B on page 150

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TIFR0 on page 158

TIMSK0 on page 157

AC - Analog Comparator on page 160

17.6.Accessing 16-bit Timer/Counter Registers

The TCNT0, OCR0A/B, and ICR0 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be accessed byte-wise, using two read or write operations. Each 16-bit timer has a single 8-bit TEMP register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer.

Accessing the low byte triggers the 16-bit read or write operation: When the low byte of a 16-bit register is written by the CPU, the high byte that is currently stored in TEMP and the low byte being written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the TEMP register in the same clock cycle as the low byte is read, and must be read subsequently.

Note:  To perform a 16-bit write operation, the low byte must be written before the high byte. For a 16-bit read, the low byte must be read before the high byte.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR0A/B 16-bit registers does not involve using the temporary register.

16-bit Access

The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B and ICR0 Registers. Note that when using C, the compiler handles the 16-bit access.

Assembly Code Example(1)

The assembly code example returns the TCNT0 value in the r17:r16 register pair.

C Code Example(1)

unsigned int i;

...

/* Set TCNT0 to 0x01FF */ TCNT0 = 0x1FF;

/* Read TCNT0 into i */ i = TCNT0;

...

Note: 

1.The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

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Atomic Read

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access.

The following code examples show how to perform an atomic read of the TCNT0 Register contents. The OCR0A/B or ICR0 Registers can be ready by using the same principle.

Assembly Code Example(1)

TIM16_ReadTCNT0:

; Save global interrupt flag in r18,SREG

;Disable interrupts cli

;Read TCNT0 into r17:r16

; Restore global interrupt flag out SREG,r18

ret

The assembly code example returns the TCNT0 value in the r17:r16 register pair.

C Code Example(1)

unsigned int TIM16_ReadTCNT0( void )

{

unsigned char sreg; unsigned int i;

/* Save global interrupt flag */ sreg = SREG;

/* Disable interrupts */ _CLI();

/* Read TCNT0 into i */ i = TCNT0;

/* Restore global interrupt flag */ SREG = sreg;

return i;

}

Note: 

1.The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

Atomic Write

The following code examples show how to do an atomic write of the TCNT0 Register contents. Writing any of the OCR0A/B or ICR0 Registers can be done by using the same principle.

Assembly Code Example(1)

TIM16_WriteTCNT0:

; Save global interrupt flag in r18,SREG

;Disable interrupts cli

;Set TCNT0 to r17:r16

; Restore global interrupt flag

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