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Signal |
PB1/ADC5/INT0/XCK0/CLKO/OC0A/PCINT9 |
PB0/ADC4/PCINT8 |
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Name |
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DDOV |
CLKO + |
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• OC0A Enable • |
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• OC0A) + |
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• |
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0 |
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(CKOUT |
REMAP |
(CKOUT |
(OC0A |
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Enable |
+ REMAP) • XCK0_MASTER • XCK0_OUT) |
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PVOE |
CKOUT(1) |
0 |
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PVOV |
(system clock) |
0 |
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PTOE |
0 |
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0 |
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DIEOE |
(PCINT9 • PCIE1) + ADC5D + INT0 |
(PCINT8 • PCIE1) + ADC4D |
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DIEOV |
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(PCINT9 • PCIE1) + INT0 |
(PCINT8 • PCIE1) |
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DI |
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INT0/PCINT1 Input |
PCINT8 Input |
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AIO |
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ADC5 |
ADC4 |
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Note:
1.CKOUT is 1 when the configuration bit is “0” (Programmed).
14.5.Register Description
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
79 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
14.5.1.Port A Input Pins Address
Name: PINA Offset: 0x00 Reset: N/A
Property:
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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PINA7 |
PINA6 |
PINA5 |
PINA4 |
PINA3 |
PINA2 |
PINA1 |
PINA0 |
Access |
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R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
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Reset |
x |
x |
x |
x |
x |
x |
x |
x |
Bits 7:0 – PINAn: Port A Input Pins Address [n = 7:0]
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
80 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
14.5.2.Port A Data Direction Register
Name: DDRA Offset: 0x01 Reset: 0x00
Property:
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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DDRA7 |
DDRA6 |
DDRA5 |
DDRA4 |
DDRA3 |
DDRA2 |
DDRA1 |
DDRA0 |
Access |
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R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
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Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bits 7:0 – DDRAn: Port A Input Pins Address [n = 7:0]
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
81 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
14.5.3.Port A Data Register
Name: PORTA Offset: 0x02 Reset: 0x00
Property:
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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PORTA7 |
PORTA6 |
PORTA5 |
PORTA4 |
PORTA3 |
PORTA2 |
PORTA1 |
PORTA0 |
Access |
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R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
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Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bits 7:0 – PORTAn: Port A Data [n = 7:0]
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
82 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
14.5.4.Port A Pull-up Enable Control Register
Name: PUEA Offset: 0x03 Reset: 0x00
Property:
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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PUEA7 |
PUEA6 |
PUEA5 |
PUEA4 |
PUEA3 |
PUEA2 |
PUEA1 |
PUEA0 |
Access |
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R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
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Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bits 7:0 – PUEAn: Port A Input Pins Address [n = 7:0]
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
83 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016