Assembly Code Example
...
;Define pull-ups and set outputs high
;Define directions for port pins
ldi r16,(1<<PUEB2) ldi r17,(1<<PB0)
ldi r18,(1<<DDB1)|(1<<DDB0) out PUEB,r16
out PORTB,r17 out DDRB,r18
;Insert nop for synchronization nop
;Read port pins
in r16,PINB
...
14.4.8.Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. The following figure shows how the port pin control signals from the simplified in the figure of Ports as General Digital I/O can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
70 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
Figure 14-6. Alternate Port Functions
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PUOExn |
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REx |
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1 |
PUOVxn |
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0 |
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Q |
D |
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PUExn |
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DDOExn |
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Q CLR |
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RESET |
WEx |
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DDOVxn |
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1 |
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0 |
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Q |
D |
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DDxn |
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Q CLR |
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PVOExn |
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RESET |
WDx |
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PVOVxn |
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RDx |
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Pxn |
1 |
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1 |
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0 |
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Q D |
0 |
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PORTxn |
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PTOExn |
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DIEOExn |
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Q CLR |
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DIEOVxn |
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RESET |
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WPx |
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1 |
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WRx |
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RRx |
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0 |
SLEEP |
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SYNCHRONIZER |
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RPx |
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D SET Q |
D |
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Q |
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PINxn |
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L CLR Q |
CLR |
Q |
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clk I/O |
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DIxn |
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AIOxn |
PUOExn: |
Pxn PULL-UPOVERRIDE ENABLE |
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WEx: |
WRITE PUEx |
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REx: |
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READ PUEx |
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PUOVxn: |
Pxn PULL-UPOVERRIDE VALUE |
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WDx: |
WRITE DDRx |
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DDOExn: |
Pxn DATA DIRECTION OVERRIDE ENABLE |
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RDx: |
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READ DDRx |
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DDOVxn: |
Pxn DATA DIRECTION OVERRIDE VALUE |
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RRx: |
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READ PORTx REGISTER |
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PVOExn: |
Pxn PORTVALUE OVERRIDE ENABLE |
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WRx: |
WRITE PORTx |
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PVOVxn: |
Pxn PORTVALUE OVERRIDE VALUE |
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RPx: |
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READ PORTx PIN |
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DIEOExn: |
Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE |
WPx: |
WRITE PINx |
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DIEOVxn: |
Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE |
clk |
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I/O CLOCK |
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SLEEP: |
SLEEPCONTROL |
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I/O |
DIGITAL INPUTPIN n ON PORTx |
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DIxn: |
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PTOExn: |
Pxn, PORTTOGGLE OVERRIDE ENABLE |
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AIOxn: |
ANALOGINPUT/OUTPUTPIN n ON PORTx |
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DATA BUS
Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O and SLEEP are common to all ports. All other signals are unique for each pin.
The following table summarizes the function of the overriding signals. The pin and port indexes from previous figure are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
71 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
Table 14-2. Generic Description of Overriding Signals for Alternate Functions
Signal Name |
Full Name |
Description |
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PUOE |
Pull-up Override |
If this signal is set, the pull-up enable is controlled by the PUOV signal. |
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Enable |
If this signal is cleared, the pull-up is enabled when PUExn = 0b1. |
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PUOV |
Pull-up Override Value |
If PUOE is set, the pull-up is enabled/disabled when PUOV is set/ |
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cleared, regardless of the setting of the PUExn Register bit. |
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DDOE |
Data Direction |
If this signal is set, the Output Driver Enable is controlled by the DDOV |
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Override Enable |
signal. If this signal is cleared, the Output driver is enabled by the DDxn |
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Register bit. |
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DDOV |
Data Direction |
If DDOE is set, the Output Driver is enabled/disabled when DDOV is |
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Override Value |
set/cleared, regardless of the setting of the DDxn Register bit. |
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PVOE |
Port Value Override |
If this signal is set and the Output Driver is enabled, the port value is |
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Enable |
controlled by the PVOV signal. If PVOE is cleared, and the Output |
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Driver is enabled, the port Value is controlled by the PORTxn Register |
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bit. |
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PVOV |
Port Value Override |
If PVOE is set, the port value is set to PVOV, regardless of the setting of |
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Value |
the PORTxn Register bit. |
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PTOE |
Port Toggle Override |
If PTOE is set, the PORTxn Register bit is inverted. |
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Enable |
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DIEOE |
Digital Input Enable |
If this bit is set, the Digital Input Enable is controlled by the DIEOV |
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Override Enable |
signal. If this signal is cleared, the Digital Input Enable is determined by |
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MCU state (Normal mode, sleep mode). |
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DIEOV |
Digital Input Enable |
If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/ |
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Override Value |
cleared, regardless of the MCU state (Normal mode, sleep mode). |
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DI |
Digital Input |
This is the Digital Input to alternate functions. In the figure, the signal is |
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connected to the output of the Schmitt Trigger but before the |
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synchronizer. Unless the Digital Input is used as a clock source, the |
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module with the alternate function will use its own synchronizer. |
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AIO |
Analog Input/Output |
This is the Analog Input/output to/from alternate functions. The signal is |
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connected directly to the pad, and can be used bi-directionally. |
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The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.
14.4.8.1.Alternate Functions of Port A
The Port A pins with alternate functions are shown in the table below:
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
72 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
Table 14-3. Port A Pins Alternate Functions
Port Pin |
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Alternate Functions |
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PA[0] |
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ADC0: ADC Input Channel 0 |
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AIN0: Analog Comparator, Positive Input |
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T0: Timer/Counter0 Clock Source (default location) |
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PCINT0: Pin Change Interrupt source 0 |
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CLKI: External Clock |
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TPICLK: Serial Programming Clock |
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PA[1] |
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ADC1: ADC Input Channel 1 |
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AIN1: Analog Comparator, Negative Input |
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OC0B: Timer/Counter0 Compare Match B Output (default |
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location) |
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PCINT1: Pin Change Interrupt source 1 |
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TPIDATA: Serial Programming Data |
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PA[2] |
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PCINT2: Pin Change Interrupt source 2 |
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Reset Pin |
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RESET: |
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PA[3] |
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OC0A: Timer/Counter0 Compare Match A Output (alternative |
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location) |
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PCINT3: Pin Change Interrupt source 3 |
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PA[4] |
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ICP0: Timer/Counter0 Input Capture Input (alternative |
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location) |
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PCINT4: Pin Change Interrupt source 4 |
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PA[5] |
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ADC2: ADC Input Channel 2 |
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OC0B: Timer/Counter0 Compare Match B Output (alternative |
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location) |
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PCINT5: Pin Change Interrupt source 5 |
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PA[6] |
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ADC3: ADC Input Channel 3 |
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PCINT6: Pin Change Interrupt source 6 |
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PA[7] |
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PCINT7: Pin Change Interrupt source 7 |
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The alternate pin configuration is as follows:
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
73 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
•PA[0] – ADC0/AIN0/T0/PCINT0/CLKI/TPICLK
–ADC0: Analog to Digital Converter, Channel 0.
–AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pullup switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
–T0: Timer/Counter0 counter source.
–PCINT0: Pin Change Interrupt source 0. The PA[0] pin can serve as an external interrupt source for pin change interrupt 0.
–CLKI: External Clock.
–TPICLK: Serial Programming Clock.
•PA[1] – ADC1/AIN1/OC0B/PCINT1/TPIDATA
–ADC1: Analog to Digital Converter, Channel 1.
–AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
–OC0B: Output Compare Match B Output. The PA[1] pin can serve as an external output for the Timer/Counter0 Compare Match B. The PA[1] pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.
–PCINT1: Pin Change Interrupt source 1. The PA[1] pin can serve as an external interrupt source for pin change interrupt 0.
–TPIDATA: Serial Programming Data.
•PA[2] – PCINT2/RESET
–PCINT2: Pin Change Interrupt source 2. The PA[2] pin can serve as an external interrupt source for pin change interrupt 0.
–RESET: Reset Pin.
•PA[3] – OC0A/PCINT3
–OC0A: Output Compare Match A Output. The PA[3] pin can serve as an external output for the Timer/Counter0 Compare Match A. The pin has to be configured as an output (DDB0 set (one)) to serve this function. This is also the output pin for the PWM mode timer function.
–PCINT3: Pin Change Interrupt source 3. The PA[3] pin can serve as an external interrupt source for pin change interrupt 0.
•PA[4] - ICP0/PCINT4
–ICP0: Input Capture Pin. The PA[4] pin can act as an Input Capture pin for Timer/Counter0.
–PCINT4: Pin Change Interrupt source 4. The PA4 pin can serve as an external interrupt source for pin change interrupt 0.
•PA[5] - ADC2/OC0B/PCINT5
–ADC2: Analog to Digital Converter, Channel 2.
–OC0B: Output Compare Match B Output: The PA1 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PA[5] pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.
–PCINT5: Pin Change Interrupt source 5. The PA5 pin can serve as an external interrupt source for pin change interrupt 0.
•PA[6] - ADC3/PCINT6
–ADC3: Analog to Digital Converter, Channel 3.
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
74 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016
–PCINT6: Pin Change Interrupt source 6. The PA6 pin can serve as an external interrupt source for pin change interrupt 0.
•PA[7] - PCINT7
–PCINT7: Pin Change Interrupt source 7. The PA7 pin can serve as an external interrupt source for pin change interrupt 0.
The following tables relate the alternate functions of Port B to the overriding signals shown in the figure of Alternate Port Functions.
Table 14-4. Overriding Signals for Alternate Functions in PA[7:6]
Signal |
PA7/PCINT7 |
PA6/ADC3/PCINT6 |
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PUOE |
0 |
0 |
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PUOV |
0 |
0 |
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DDOE |
0 |
0 |
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DDOV |
0 |
0 |
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PVOE |
0 |
0 |
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PVOV |
0 |
0 |
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PTOE |
0 |
0 |
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DIEOE |
(PCINT7 • PCIE0) |
(PCINT6 • PCIE0) + ADC3D |
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DIEOV |
PCINT7 • PCIE0 |
PCINT6 • PCIE0 |
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DI |
PCINT7 Input |
PCINT6 input |
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AIO |
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ADC3 |
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Table 14-5. Overriding Signals for Alternate Functions in PA[5:4] |
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Signal |
PA5/ADC2/OC0B/PCINT5 |
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PA4/ICP0/PCINT4 |
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Name |
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PUOE |
0 |
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0 |
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PUOV |
0 |
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0 |
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DDOE |
0 |
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0 |
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DDOV |
0 |
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0 |
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PVOE |
(OC0B Enable • REMAP) |
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0 |
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PVOV |
(OC0B • REMAP) |
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0 |
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PTOE |
0 |
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0 |
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DIEOE |
(PCINT5 • PCIE0) + ADC2D |
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(PCINT4 • PCIE0) |
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DIEOV |
PCINT5 • PCIE0 |
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(PCINT4 • PCIE0) |
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DI |
PCINT5 Input |
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ICP0/PCINT4 Input |
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AIO |
ADC2 |
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- |
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Atmel ATtiny102 / ATtiny104 [DATASHEET] |
75 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016