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0x002 |
|
rjmp PCINT0 |
; PCINT0 |
Handler |
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0x003 |
|
rjmp PCINT1 |
; PCINT1 Handler |
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0x004 |
|
rjmp TIM0_CAPT |
; Timer/Counter0 Capture Handler |
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0x005 |
|
rjmp TIM0_OVF |
; Timer/Counter0 Overflow Handler |
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0x006 |
|
rjmp TIM0_COMPA |
; Timer/Counter0 Compare Match A Handler |
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0x007 |
|
rjmp TIM0_COMPB |
; Timer/Counter0 Compare Match B Handler |
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0x008 |
|
rjmp ANA_COMP |
; Analog Comparator Handler |
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0x009 |
|
rjmp WDT |
; Watchdog Timer Handler |
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0x00A |
|
rjmp VLM |
; Voltage Level Monitor Handler |
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0x00B |
|
rjmp ADC |
; ADC Conversion Handler |
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0x00C |
|
rjmp USART0_RXS |
; USART0 Rx Start Handler |
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0x00D |
|
rjmp USART0_RXC |
; USART0 Rx Complete Handler |
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0x00E |
|
rjmp USART0_DRE |
; USART0 Data Register Empty Handler |
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0x00F |
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rjmp USART0_TXC |
; USART0 Tx Complete Handler |
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0x010 |
RESET: |
ldi r16, high (RAMEND) |
; Main program start |
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0x011 |
|
out SPH, r16 |
; Set Stack Pointer |
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0x012 |
|
ldi r16, low(RAMEND) |
; to top of RAM |
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0x013 |
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out SPL, r16 |
; Enable interrupts |
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0x014 |
|
sei |
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||
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0x015 |
|
<instr> |
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... |
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... |
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13.3.External Interrupts
The External Interrupts are triggered by the INT0 pins or any of the PCINT[11:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT[11:0] pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI0 will trigger if any enabled PCINT[11:0] pin toggles. The Pin Change Mask 0/1 Register (PCMSK 0/1) controls which pins contribute to the pin change interrupts. Pin change interrupts on PCINT[11:0] are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Register A (EICRA). When the INT0 interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in Clock Systems and their Distribution chapter.
Related Links
Clock System on page 30
EICRA on page 58
PCMSK0 on page 63
PCMSK1 on page 64
13.3.1.Low Level Interrupt
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle).
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined as described in Clock System
If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command.
Related Links
Atmel ATtiny102 / ATtiny104 [DATASHEET] |
56 |
Atmel-42505D-ATtiny102-ATtiny104_Datasheet_Complete-10/2016