лаб2 / module ALUcont(

module ALUcont(
input logic [31:0] a_i,
input logic [31:0] b_i,
input logic [4:0] alu_op_i,
output logic flag_o,
output logic [31:0] result_o
);

//импорт опкодов операций
import alu_opcodes_pkg::*;
logic [31:0] sum_result;
logic sum_dummy_carry;

fulladder32 adder_inst(

.a_i(a_i[31:0]),
.b_i(b_i[31:0]),
.carry_i(1'b0),
.sum_o(sum_result),
.carry_o(sum_dummy_carry)
);
//логика вычисления result_o
always_comb begin
result_o = '0;
case (alu_op_i)
ALU_ADD : result_o = sum_result;
ALU_SUB : result_o = a_i - b_i;
ALU_XOR : result_o = a_i ^ b_i;
ALU_OR : result_o = a_i | b_i ;
ALU_AND : result_o = a_i & b_i ;
ALU_SRA : result_o = $signed(a_i)>>>b_i[4:0];
ALU_SRL : result_o = a_i >> b_i[4:0] ;
ALU_SLL : result_o = a_i << b_i[4:0] ;
ALU_SLTS: result_o ={31'd0, ($signed(a_i)<$signed(b_i))};
ALU_SLTU: result_o = {31'd0, (a_i<b_i)} ;
default : result_o = '0;
endcase
end

always_comb begin
flag_o = 1'b0;
case (alu_op_i)
ALU_LTS : flag_o = $signed(a_i < b_i);
ALU_LTU : flag_o = a_i < b_i ;
ALU_GES : flag_o = $signed(a_i) >= $signed(b_i);
ALU_GEU : flag_o = a_i >= b_i;
ALU_EQ : flag_o = (a_i == b_i);
ALU_NE : flag_o = (a_i != b_i);
default flag_o = 1'b0;
endcase
end

endmodule


//добавление элементов из прошлой лабы
module fulladder32(
input [31:0]a_i,
input [31:0]b_i,
input carry_i,
output [31:0]sum_o,
output carry_o
);

wire [6:0]c ;
fulladder4 f1(.a_i(a_i[3:0]), .b_i(b_i[3:0]), .carry_i(carry_i), .sum_o(sum_o[3:0]), .carry_o(c[0]));
fulladder4 f2(.a_i(a_i[7:4]), .b_i(b_i[7:4]), .carry_i(c[0]), .sum_o(sum_o[7:4]), .carry_o(c[1]));
fulladder4 f3(.a_i(a_i[11:8]), .b_i(b_i[11:8]), .carry_i(c[1]), .sum_o(sum_o[11:8]), .carry_o(c[2]));
fulladder4 f4(.a_i(a_i[15:12]), .b_i(b_i[15:12]), .carry_i(c[2]), .sum_o(sum_o[15:12]), .carry_o(c[3]));
fulladder4 f5(.a_i(a_i[19:16]), .b_i(b_i[19:16]), .carry_i(c[3]), .sum_o(sum_o[19:16]), .carry_o(c[4]));
fulladder4 f6(.a_i(a_i[23:20]), .b_i(b_i[23:20]), .carry_i(c[4]), .sum_o(sum_o[23:20]), .carry_o(c[5]));
fulladder4 f7(.a_i(a_i[27:24]), .b_i(b_i[27:24]), .carry_i(c[5]), .sum_o(sum_o[27:24]), .carry_o(c[6]));
fulladder4 f8(.a_i(a_i[31:28]), .b_i(b_i[31:28]), .carry_i(c[6]), .sum_o(sum_o[31:28]), .carry_o(carry_o));

endmodule

module Andd(

input A,
input B,
output C);
assign C = A&B;
endmodule

module Orr(

input A,
input B,
output C);
assign C = A|B;
endmodule

module Xorr(

input A,
input B,
output C);
assign C = A^B;
endmodule

module fulladder(
input a_i,
input b_i,
input carry_i,
output sum_o,
output carry_o);

logic q, w, e, r, t,y;
Xorr moduleXOR1(.A(a_i), .B(b_i), .C(q));
Xorr moduleXOR2(.A(q), .B(carry_i), .C(sum_o));
Andd moduleAND1(.A(a_i), .B(carry_i), .C(w));
Andd moduleAND2(.A(a_i), .B(b_i), .C(e));
Andd moduleAND3(.A(carry_i), .B(b_i), .C(r));
Orr moduleOR1(.A(w), .B(e), .C(t));
Orr moduleOR2(.A(t), .B(r), .C(carry_o));
endmodule

module fulladder4(
input logic [3:0]a_i,
input logic [3:0]b_i,
input logic carry_i,
output logic [3:0]sum_o,
output logic carry_o );

logic a1, a2, a3;

fulladder fa1(.a_i(a_i[0]), .b_i(b_i[0]), .carry_i(carry_i), .sum_o(sum_o[0]), .carry_o(a1));
fulladder fa2(.a_i(a_i[1]), .b_i(b_i[1]), .carry_i(a1), .sum_o(sum_o[1]), .carry_o(a2));
fulladder fa3(.a_i(a_i[2]), .b_i(b_i[2]), .carry_i(a2), .sum_o(sum_o[2]), .carry_o(a3));
fulladder fa4(.a_i(a_i[3]), .b_i(b_i[3]), .carry_i(a3), .sum_o(sum_o[3]), .carry_o(carry_o));
endmodule