lab5 / lr5_2

set file_name "adder.vhdl"
set adder_bus "adder_bus.vhdl"
set adder_single_bit "adder_single_bit.vhdl"
#set file_name "lr5_1.tcl"
#puts $file_name

set a [open $file_name]
set lines [split [read $a] "\n"]
close $a;

set ab [open $adder_bus w]
set asb [open $adder_single_bit w]

#puts [llength $lines]
#puts [lindex $lines end]
set lines [lreplace $lines end end]
#puts [llength $lines]


foreach line $lines {
# do something with each line...

if {[string match "*(* downto *);" $line]} {
set trimmed_line [string trim $line]

set first_space [string first " " $trimmed_line]
set v_name [string range $trimmed_line 0 [expr {$first_space - 1}]]

#append part_one [string range $hex_string 0 [expr {$first_f_index - 1}]]

#puts $trimmed_line
#puts $v_name
set range_name [string first ":" $trimmed_line]
set name [string range $trimmed_line 0 $range_name-2]
set rest [string range $trimmed_line $range_name-1 end]
puts $name
puts $rest

set range_start [string first "(" $trimmed_line]
set range_declaration [string range $trimmed_line [expr {$range_start+2 - 1}] end]
puts $range_declaration

set first_space_range [string first " " $range_declaration]
set top_index [string range $range_declaration 0 $first_space_range-1]
puts $top_index

set last_space_range [string last " " $range_declaration]
set range_end [string first ")" $range_declaration]
set bottom_index [string range $range_declaration $last_space_range+1 $range_end-1]
puts $bottom_index

set bus_line " ${name}_bus_${top_index}_${bottom_index}$rest"
puts $ab "$bus_line"
#append new_name "_$top_index"
#append new_name "_$bottom_index"
#puts $bus_line
#append new_name "$name"
set type_bus [string first "_vector" $rest]
set type [string range $rest 0 [expr {$type_bus - 1}]]

#_$top_index_$bottom_index

for { set i $top_index } { $i>= $bottom_index} { incr i -1 } {

puts $asb " ${name}_${i}${type};"

}






} else {

puts $ab "$line"
puts $asb "$line"

}



}

close $ab
close $asb