5.3.3DDR testing

Prerequisites

To proceed with DDR testing:

•The DDR suite must be in connected state

•The DDR configuration must be available in memory, either with the U-Boot SPL (with DDR register file in Device Tree) or in the DDR registers (see Section 5.3.2).

DDR test list

DDR tests are part of the U-Boot SPL (see Figure 275).

Figure 275. DDR test list from U-Boot SPL

New tests can be added by modifying the U-boot SPL.

Most of the tests come with parameters to be set prior to execution, such as:

•Address: the memory address where the test is executed. All writes and reads are performed on this address. The given address has to be located in the DDR memory region [DDR base address, DDR base address + DDR size].

•On STM32MP15, DDR base address is 0xC0000000 (as an example, DDR size for 4 Gbits is 0x20000000).

•Loop: number of test iterations before verdict. Same test is repeated [Loop] times. Verdict OK if all tests are OK, KO otherwise.

•Size: the byte size of the region to test. Size must be a multiple of 4 (read/writes are performed on 32-bit unsigned integers) with minimal value equal to 4. Size can be up to DDR size.

•Pattern: the 32-bit pattern to be used for read / write operations.

The DDR Suite embeds an auto-correction feature preventing users to specify wrong values.

All tests are performed with Data cache disabled and Instruction cache enabled.

DDR test results

The test verdict is reported by the U-Boot SPL: the parameters used for the tests are recalled, along with Pass/Fail status and results details (see Figure 276). The test history is available in the output and Logs panels (see Figure 277).

Figure 276. DDR test suite results

Figure 277. DDR tests history