DDR Test suite testing and tuning features are available from the Tools view. The DDR suite relies on two important concepts:

•the DDR timings as key inputs for the configuration of the DDR Controller and PHY

•the tuning of DDR signals to compensate board design imperfections.

5.3.1DDR configuration

STM32CubeMX allows to set DDR system parameters and JEDEC core timings. The timing parameters are available in the DDR datasheet.

DDR type, width and density

The DDR type, width and density parameter settings are required to proceed with the DDR configuration step. This can be done in the mode panel after selecting the DDR in the

Pinout & Configuration view.

See Figure 268 for an example of LPDDR2 settings.

Figure 268. DDR pinout and configuration settings

DDR configuration

Clicking on a parameter will show additional details in the DDR configuration footer.

•The DDR frequency is taken from the ‘Clock configuration’ tab, it cannot be changed in the DDR configuration.

•The ‘Relaxed Timing’ mode is used during bring-up phase for trying relaxed key DDR timings value (one tCK added to tRC, tRCD and tRP timings)

•Other parameters must be retrieved from the user DDR datasheet.

•Some parameters are read-only: they are for information only and depend on the DDR type.

Clicking “generate code” automatically computes the DDR node of the device tree (DDR Controller and DDR PHY registers values) based on these parameters.

DDR3 configuration

For DDR3, the configuration is made easier with the selection of a Speed Bin / Grade combination, instead of manually editing timing parameters.

Figure 269. DDR3 configuration

The Speed Bin / Grade combination must match the selected DDR. If the exact combination is not in the pick-list, “1066E / 6-6-6” must be selected for faster DDR Speed bin / Grade, whereas “1066G / 8-8-8” can be used as a relaxed configuration.