- •1 About this document
- •1.1 Typographical conventions
- •1.2 List of abbreviations for registers
- •Figure 1. STM32 Cortex®-M7 implementation processor
- •1.3.1 System level interface
- •1.3.2 Integrated configurable debug
- •2 The Cortex-M7 processor
- •2.1 Programmers model
- •2.1.1 Processor mode and privilege levels for software execution
- •2.1.2 Stacks
- •2.1.3 Core registers
- •Figure 2. Processor core registers
- •Table 2. Core register set summary
- •Figure 3. APSR, IPSR and EPSR bit assignments
- •Table 3. PSR register combinations
- •Table 4. APSR bit assignments
- •Table 5. IPSR bit assignments
- •Table 6. EPSR bit assignments
- •Figure 4. PRIMASK bit assignments:
- •Table 7. PRIMASK register bit assignments
- •Figure 5. FAULTMASK bit assignments
- •Table 8. FAULTMASK register bit assignments
- •Figure 6. BASEPRI bit assignments
- •Table 9. BASEPRI register bit assignments
- •Figure 7. Control bit assignments
- •2.1.4 Exceptions and interrupts
- •2.1.5 Data types
- •2.1.6 The Cortex Microcontroller Software Interface Standard (CMSIS)
- •Table 11. STM32F746xx/STM32F756xx Cortex®-M7 configuration
- •Table 12. STM32F76xxx/STM32F77xxx Cortex®-M7 configuration
- •Table 13. STM32F72xxx/STM32F73xxx Cortex®-M7 configuration
- •Table 14. STM32H7 Series Cortex®-M7 configuration
- •2.3 Memory model
- •Figure 8. Processor memory map
- •2.3.1 Memory regions, types and attributes
- •2.3.2 Memory system ordering of memory accesses
- •Table 15. Ordering of memory accesses
- •2.3.3 Behavior of memory accesses
- •Table 16. Memory access behavior
- •Table 17. Memory region shareability and cache policies
- •2.3.4 Software ordering of memory accesses
- •2.3.5 Memory endianness
- •Figure 9. Little-endian format
- •2.3.6 Synchronization primitives
- •2.3.7 Programming hints for the synchronization primitives
- •Table 18. CMSIS functions for exclusive access instructions
- •2.4 Exception model
- •2.4.1 Exception states
- •2.4.2 Exception types
- •2.4.3 Exception handlers
- •2.4.4 Vector table
- •Figure 10. Vector table
- •2.4.5 Exception priorities
- •2.4.6 Interrupt priority grouping
- •2.4.7 Exception entry and return
- •Figure 11. Exception stack frame
- •Table 20. Exception return behavior
- •2.5 Fault handling
- •2.5.1 Fault types
- •2.5.2 Fault escalation and hard faults
- •2.5.3 Synchronous and Asynchronous bus faults
- •2.5.4 Fault status registers and fault address registers
- •Table 22. Fault status and fault address registers
- •2.5.5 Lockup
- •2.6 Power management
- •2.6.1 Entering sleep mode
- •2.6.2 Wakeup from sleep mode
- •2.6.3 The external event input
- •2.6.4 Power management programming hints
- •3 The Cortex-M7 instruction set
- •3.1 Instruction set summary
- •3.1.1 Binary compatibility with other Cortex processors
- •3.2 CMSIS functions
- •Table 24. CMSIS functions to generate some Cortex®-M7 processor instructions
- •Table 25. CMSIS functions to access the special registers
- •3.3 About the instruction descriptions
- •3.3.1 Operands
- •3.3.2 Restrictions when using PC or SP
- •3.3.3 Flexible second operand
- •3.3.4 Shift operations
- •Figure 12. ASR
- •Figure 13. LSR
- •Figure 14. LSL
- •Figure 15. ROR
- •Figure 16. RRX
- •3.3.5 Address alignment
- •3.3.7 Conditional execution
- •Table 26. Condition code suffixes
- •3.3.8 Instruction width selection
- •3.4 Memory access instructions
- •Table 27. Memory access instructions
- •3.4.2 LDR and STR, immediate offset
- •Table 28. Offset ranges
- •3.4.3 LDR and STR, register offset
- •3.4.4 LDR and STR, unprivileged
- •Table 29. Offset ranges
- •3.4.8 PUSH and POP
- •3.4.9 LDREX and STREX
- •3.4.10 CLREX
- •3.5 General data processing instructions
- •3.5.7 MOVT
- •3.5.8 REV, REV16, REVSH, and RBIT
- •3.5.9 SADD16 and SADD8
- •3.5.10 SHADD16 and SHADD8
- •3.5.11 SHASX and SHSAX
- •3.5.12 SHSUB16 and SHSUB8
- •3.5.13 SSUB16 and SSUB8
- •3.5.14 SASX and SSAX
- •3.5.16 UADD16 and UADD8
- •3.5.17 UASX and USAX
- •3.5.18 UHADD16 and UHADD8
- •3.5.19 UHASX and UHSAX
- •3.5.20 UHSUB16 and UHSUB8
- •3.5.22 USAD8
- •3.5.23 USADA8
- •3.5.24 USUB16 and USUB8
- •3.6 Multiply and divide instructions
- •3.6.2 UMULL, UMAAL, UMLAL
- •3.6.3 SMLA and SMLAW
- •3.6.4 SMLAD
- •3.6.5 SMLAL and SMLALD
- •3.6.6 SMLSD and SMLSLD
- •3.6.7 SMMLA and SMMLS
- •3.6.8 SMMUL
- •3.6.9 SMUAD and SMUSD
- •3.6.10 SMUL and SMULW
- •3.6.11 UMULL, UMLAL, SMULL, and SMLAL
- •3.6.12 SDIV and UDIV
- •3.7 Saturating instructions
- •Table 32. Saturating instructions
- •3.7.1 SSAT and USAT
- •3.7.2 SSAT16 and USAT16
- •3.7.3 QADD and QSUB
- •3.7.4 QASX and QSAX
- •3.7.5 QDADD and QDSUB
- •3.7.6 UQASX and UQSAX
- •3.7.7 UQADD and UQSUB
- •3.8 Packing and unpacking instructions
- •Table 33. Packing and unpacking instructions
- •3.8.1 PKHBT and PKHTB
- •3.8.3 SXTA and UXTA
- •3.9 Bit field instructions
- •Table 34. Packing and unpacking instructions
- •3.9.2 SBFX and UBFX
- •3.10 Branch and control instructions
- •Table 35. Branch and control instructions
- •Table 36. Branch ranges
- •3.10.2 CBZ and CBNZ
- •3.11.1 VABS
- •3.11.2 VADD
- •3.11.3 VCMP, VCMPE
- •3.11.6 VCVTB, VCVTT
- •3.11.7 VDIV
- •3.11.8 VFMA, VFMS
- •3.11.9 VFNMA, VFNMS
- •3.11.10 VLDM
- •3.11.11 VLDR
- •3.11.12 VMLA, VMLS
- •3.11.13 VMOV immediate
- •3.11.14 VMOV register
- •3.11.15 VMOV scalar to Arm core register
- •3.11.19 VMOV Arm core register to scalar
- •3.11.20 VMRS
- •3.11.21 VMSR
- •3.11.22 VMUL
- •3.11.23 VNEG
- •3.11.24 VNMLA, VNMLS, VNMUL
- •3.11.25 VPOP
- •3.11.26 VPUSH
- •3.11.27 VSQRT
- •3.11.28 VSTM
- •3.11.29 VSTR
- •3.11.30 VSUB
- •3.11.31 VSEL
- •3.11.32 VMAXNM, VMINNM
- •3.11.33 VCVTA, VCVTN, VCVTP, VCVTM
- •3.11.34 VRINTR, VRINTX
- •3.11.35 VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ
- •3.12 Miscellaneous instructions
- •Table 38. Miscellaneous instructions
- •3.12.1 BKPT
- •4 Cortex-M7 peripherals
- •Table 39. Core peripheral register regions
- •4.2 Nested Vectored Interrupt Controller
- •Table 40. NVIC register summary
- •Table 41. CMSIS access NVIC functions
- •Figure 17. ISER bit assignments
- •Table 42. ISER bit assignments
- •Figure 18. ICER bit assignment
- •Table 43. ICER bit assignments
- •Figure 19. ISPR bit assignments
- •Table 44. ISPR bit assignments
- •Figure 20. ICPR bit assignments
- •Table 45. ICPR bit assignments
- •4.2.6 Interrupt active bit registers
- •Figure 21. IABR bit assignments
- •Table 46. IABR bit assignments
- •4.2.7 Interrupt priority registers
- •Figure 22. IPR bit assignments
- •Table 47. IPR bit assignments
- •4.2.8 Software trigger interrupt register
- •Figure 23. STIR bit assignments
- •Table 48. STIR bit assignments
- •4.2.10 NVIC design hints and tips
- •Table 49. CMSIS functions for NVIC control
- •4.3 System control block
- •Table 50. Summary of the system control block registers
- •4.3.1 Auxiliary control register
- •Figure 24. ACTLR bit assignments
- •Table 51. ACTLR bit assignments
- •4.3.2 CPUID base register
- •Figure 25. CPUID bit assignments
- •Table 52. CPUID bit assignments
- •4.3.3 Interrupt control and state register
- •Figure 26. ICSR bit assignments
- •4.3.4 Vector table offset register
- •Figure 27. VTOR bit assignments
- •Table 54. VTOR bit assignments
- •4.3.5 Application interrupt and reset control register
- •Figure 28. AIRCR bit assignments
- •Table 55. AIRCR bit assignments
- •4.3.6 System control register
- •Figure 29. SCR bit assignments:
- •4.3.7 Configuration and control register
- •Figure 30. CCR bit assignments
- •4.3.8 System handler priority registers
- •Table 59. System fault handler priority fields
- •Figure 31. SHPR1 bit assignements
- •Table 60. SHPR1 register bit assignments
- •Figure 32. SHPR2 bit assignments
- •Table 61. SHPR2 register bit assignments
- •Figure 33. SHPR3 bit assignments
- •Table 62. SHPR3 register bit assignments
- •4.3.9 System handler control and state register
- •Figure 34. SHCSR bit assignments
- •4.3.10 Configurable fault status register
- •Figure 35. CFSR bit assignments
- •Figure 36. MMFSR bit assignments
- •Figure 37. BFSR bit assignments
- •Table 65. BFSR bit assignments
- •Figure 38. UFSR bit assignments
- •4.3.11 HardFault status register
- •Figure 39. HFSR bit assignments
- •Table 67. HFSR bit assignments
- •4.3.12 MemManage fault address register
- •Table 68. MMFAR bit assignments
- •4.3.13 BusFault address register
- •Table 69. BFAR bit assignments
- •4.3.14 System control block design hints and tips
- •Table 70. CMSIS function for system control
- •4.4 System timer, SysTick
- •Table 71. System timer registers summary
- •4.4.1 SysTick control and status register
- •Figure 40. SysTick SYST_CSR bit assignments
- •Table 72. SysTick SYST_CSR bit assignments
- •4.4.2 SysTick reload value register
- •Figure 41. SYST_RVR bit assignments
- •Table 73. SYST_RVR bit assignments
- •4.4.3 SysTick current value register
- •Figure 42. SYST_CVR bit assignments:
- •Table 74. SYST_CVR bit assignments
- •4.4.4 SysTick calibration value register
- •Figure 43. SYST_CALIB bit assignments
- •Table 75. SYST_CALIB bit assignments
- •4.4.5 SysTick design hints and tips
- •Table 76. CMSIS functions for SysTick control
- •4.5 Processor features
- •Table 77. Identification space summary
- •4.5.1 Cache level ID register
- •Figure 44. CLIDR bit assignments
- •4.5.2 Cache type register
- •Figure 45. CTR bit assignments
- •4.5.3 Cache size ID register
- •Figure 46. CCSIDR bit assignments
- •Table 80. CCSIDR bit assignments
- •Table 81. CCSIDR encodings
- •4.5.4 Cache size selection register
- •Figure 47. CSSELR bit assignments
- •Table 82. CSSELR bit assignments
- •4.6 Memory protection unit
- •Table 84. MPU registers summary
- •4.6.1 MPU type register
- •Figure 48. TYPE bit assignments
- •Table 85. TYPE bit assignments
- •4.6.2 MPU control register
- •Figure 49. MPU_CTRL bit assignments
- •Table 86. MPU_CTRL bit assignments
- •4.6.3 MPU region number register
- •Figure 50. MPU_RNR bit assignments
- •Table 87. MPU_RNR bit assignments
- •4.6.4 MPU region base address register
- •Figure 51. MPU_RBAR bit assignments:
- •Table 88. MPU_RBAR bit assignments
- •4.6.5 MPU region attribute and size register
- •Figure 52. MPU_RASR bit assignments
- •Table 89. MPU_RASR bit assignments
- •Table 90. Example SIZE field values
- •4.6.6 MPU access permission attributes
- •Table 92. Cache policy for memory attribute encoding
- •Table 93. AP encoding
- •4.6.7 MPU mismatch
- •4.6.8 Updating an MPU region
- •Figure 53. Example of disabling subregion
- •4.6.9 MPU design hints and tips
- •Table 94. Cortex®-M7 floating-point system registers
- •4.7.1 Coprocessor access control register
- •Figure 54. CPACR bit assignments
- •Table 95. CPACR bit assignments
- •Figure 55. FPCCR bit assignments
- •Figure 56. FPCAR bit assignments
- •Table 97. FPCAR bit assignments
- •Figure 57. FPSCR bit assignments
- •Figure 58. FPDSCR bit assignments
- •4.7.6 Enabling the FPU
- •4.7.7 Enabling and clearing FPU exception interrupts
- •4.8 Cache maintenance operations
- •Table 100. Cache maintenance space register summary
- •4.8.1 Full instruction cache operation
- •4.8.2 Instruction and data cache operations by address
- •Table 101. Cache operation registers bit assignments
- •Figure 59. Cache operation bit assignments
- •Table 102. Cache operations by set-way bit assignments
- •Table 103. CMSIS access cache maintenance operations
- •4.8.6 Faults handling considerations
- •4.8.7 Cache maintenance design hints and tips
- •4.9 Access control
- •Table 104. Access control register summary
- •Figure 60. ITCMR and DTCMR bit assignments
- •Table 105. ITCMCR and DTCMCR bit assignments
- •4.9.2 AHBP control register
- •Figure 61. AHBPCR bit assignments
- •Table 106. AHBPCR bit assignments
- •4.9.3 Auxiliary cache control register
- •Figure 62. CACR bit assignments
- •Table 107. CACR bit assignments
- •4.9.4 AHB slave control register
- •Figure 63. AHBSCR bit assignments
- •4.9.5 Auxiliary bus fault status register
- •Figure 64. ABFSR bit assignments
- •5 Revision history
- •Table 110. Document revision history
PM0253 |
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Cortex-M7 peripherals |
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Table 108. AHBSCR bit assignments (continued) |
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Threshold execution priority for AHBS traffic demotion. |
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0b0xxxxxxx: Priority is TPRI[7:0]. This is the same as the NVIC register |
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encodings. |
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0b11111111: Priority of -1. This is the priority of the HardFault exception. |
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0b11111110: Priority of -2. This is the priority of the NMI exception. |
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AHBS prioritization control: |
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0b00: AHBS access priority demoted. This is the reset value. |
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0b01: Software access priority demoted. |
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0b10: AHBS access priority demoted by initializing the fairness counter to the |
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AHBSCR.INITCOUNT value when the software execution priority is higher |
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software execution priority is below this value, the fairness counter is initialized |
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with 1 (round-robin). |
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The threshold level encoding matches the NVIC encoding and uses |
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arithmetically larger numbers to represent lower priority. |
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0b11: AHBSPRI signal has control of access priority. |
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4.9.5Auxiliary bus fault status register
The ABFSR stores information on the source of asynchronous bus faults. The ASBFSR bit assignments are:
Figure 64. ABFSR bit assignments
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4 |
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1 |
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Reserved |
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Reserved |
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AXIMTYPE |
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EPPB |
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AXIM |
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AHBP |
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DTCM |
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ITCM |
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MSv39647V1 |
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Table 109. ABFSR bit assignments |
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[31:10] |
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Indicates the type of fault on the AXIM interface: |
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b00: OKAY |
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AXIMTYPE |
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b01: EXOKAY |
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b10: SLVERR |
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b11: DECERR |
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Only valid when AXIM is 1. |
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[7:5] |
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[4] |
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EPPB |
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Asynchronous fault on EPPB interface. |
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PM0253 Rev 5 |
251/254 |
Cortex-M7 peripherals |
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PM0253 |
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Table 109. ABFSR bit assignments (continued) |
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Function |
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[3] |
AXIM |
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Asynchronous fault on AXIM interface. |
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[2] |
AHBP |
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Asynchronous fault on AHBP interface. |
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[1] |
DTCM |
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Asynchronous fault on DTCM interface. |
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[0] |
ITCM |
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Asynchronous fault on ITCM interface |
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In the bus-fault handler, the software reads the BFSR, and if an asynchronous fault occurs, the ABFSR is read to determine which interfaces are affected. The ABFSR[4:0] fields remains valid until cleared by writing to the ABFSR with any value.
For more information about the BFSR, see BusFault status register on page 207.
252/254 |
PM0253 Rev 5 |