PM0253 |
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Cortex-M7 peripherals |
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Table 79. CTR bit assignments (continued) |
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[13:4] |
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Reserved, RAZ. |
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Smallest cache line of all the instruction caches under the control of the |
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[3:0] |
IminLine |
processor. |
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0b0011: 8 words for the Cortex®-M7 processor. |
4.5.3Cache size ID register
The CCSIDR identifies the configuration of the cache currently selected by the CSSELR. If no instruction or data cache is configured, the corresponding CCSIDR is RAZ. See the register summary in Table 77 on page 217 for its attributes. The bit assignments are:
Figure 46. CCSIDR bit assignments
31 30 29 28 27 |
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13 12 |
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0 |
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NumSet |
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LineSize |
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WA |
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RA |
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WB |
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WT |
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MSv39657V1 |
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Table 80. CCSIDR bit assignments |
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Function(1) |
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[31] |
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WT |
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Indicates support available for Write-Through: |
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1: Write-Through support available. |
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[30] |
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WB |
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Indicates support available for Write-Back: |
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1: Write-Back support available. |
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[29] |
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RA |
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Indicates support available for read allocation: |
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1: Read allocation support available. |
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[28] |
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WA |
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Indicates support available for write allocation: |
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1: Write allocation support available. |
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[27:13] |
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NumSets |
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Indicates the number of sets as: |
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[12:3] |
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Associativity |
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Indicates the number of ways as: |
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(number of ways) - 1. |
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[2:0] |
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LineSize |
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Indicates the number of words in each cache line. |
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1. See Table 81 on page 220 for valid bit field encodings.
The LineSize field is encoded as 2 less than log(2) of the number of words in the cache line. For example, a value of 0x0 indicates there are four words in a cache line, that is the minimum size for the cache. A value of 0x1 indicates there are eight words in a cache line.
PM0253 Rev 5 |
219/254 |