3.6.9SMUAD and SMUSD

Signed Dual Multiply Add and Signed Dual Multiply Subtract.

Syntax

op{X}{cond} Rd, Rn, Rm

Operation

The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each operand. This instruction:

•Optionally rotates the halfwords of the second operand.

•Performs two signed 16 × 16-bit multiplications.

•Adds the two multiplication results together.

•Writes the result of the addition to the destination register.

The SMUSD instruction interprets the values from the first and second operands as two’s complement signed integers. This instruction:

•Optionally rotates the halfwords of the second operand.

•Performs two signed 16 × 16-bit multiplications.

•Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication.

•Writes the result of the subtraction to the destination register.

Restrictions

In these instructions:

•Do not use SP and do not use PC.

Condition flags

Sets the Q flag if the addition overflows. The multiplications cannot overflow.

Examples

;top halfword of R4 with top halfword of R5,

;writes to R0.

3.6.10SMUL and SMULW

Signed Multiply (halfwords) and Signed Multiply (word by halfword).

Syntax

op{XY}{cond} Rd,Rn, Rm

op{Y}{cond} Rd. Rn, Rm

For SMULXY only:

Operation

The SMULBB, SMULTB, SMULBT and SMULTT instructions interprets the values from Rn and Rm as four signed 16-bit integers.

These instructions:

•Multiply the specified signed halfword, Top or Bottom, values from Rn and Rm.

•Write the 32-bit result of the multiplication in Rd.

The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and Rm as two halfword 16-bit signed integers. These instructions:

•Multiply the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand.

•Write the signed most significant 32 bits of the 48-bit result in the destination register.

Restrictions

In these instructions:

•Do not use SP and do not use PC.

•RdHi and RdLo must be different registers.

Examples

3.6.11UMULL, UMLAL, SMULL, and SMLAL

Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result.

Syntax

op{cond} RdLo, RdHi, Rn, Rm

cond

RdHi, RdLo Are the destination registers. For UMLAL and SMLAL they also hold the accumulating value.

Rn, Rm Are registers holding the operands.

Operation

The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo.

The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo.

Restrictions

In these instructions:

•Do not use SP and do not use PC.

•RdHi and RdLo must be different registers.

Condition flags

These instructions do not affect the condition code flags.

Examples